diff --git a/mips_cpu/testbench.sv b/mips_cpu/testbench.sv
index 9cb429f..0a2f6fe 100644
--- a/mips_cpu/testbench.sv
+++ b/mips_cpu/testbench.sv
@@ -94,6 +94,8 @@ module testbench ();
 
 		// Wait for the mips_core to report a fail or done MTC0 instruction
 		wait(DUT.pass_done.code == MTC0_FAIL || DUT.pass_done.code == MTC0_DONE);
+		$display("%m (%t) #Instructions = %d, #Cycles = %d",
+			$time, DUT.MIPS_CORE.num_instructions, DUT.MIPS_CORE.num_cycles);
 		$stop;
 	end
 endmodule