From 1329579e042995ecabcf7ee9905d63d1e751b0ae Mon Sep 17 00:00:00 2001 From: zinsser Date: Fri, 13 Apr 2018 00:32:19 -0700 Subject: [PATCH] Report the number of instructions and the number of cycles at the end of a full simulation. --- mips_cpu/testbench.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mips_cpu/testbench.sv b/mips_cpu/testbench.sv index 9cb429f..0a2f6fe 100644 --- a/mips_cpu/testbench.sv +++ b/mips_cpu/testbench.sv @@ -94,6 +94,8 @@ module testbench (); // Wait for the mips_core to report a fail or done MTC0 instruction wait(DUT.pass_done.code == MTC0_FAIL || DUT.pass_done.code == MTC0_DONE); + $display("%m (%t) #Instructions = %d, #Cycles = %d", + $time, DUT.MIPS_CORE.num_instructions, DUT.MIPS_CORE.num_cycles); $stop; end endmodule -- 1.9.1