diff --git a/mips_cpu/synth/Makefile b/mips_cpu/synth/Makefile
index 7ab3c89..5f8af00 100644
--- a/mips_cpu/synth/Makefile
+++ b/mips_cpu/synth/Makefile
@@ -5,6 +5,8 @@ ifneq (clean,$(MAKECMDGOALS))
 include configs.mk
 endif
 
+open_RAM=OpenRAM-1.2.46
+
 ram_targets=$(configs:%=build/sram_%_freepdk45_analytical_TT_1p0V_25C.lib)
 
 all: netlist.v
@@ -23,9 +25,9 @@ rams: $(ram_targets)
 build/sram_%_freepdk45_analytical_TT_1p0V_25C.lib : config.py
 	env RAM_CONFIG="$*" \
 		FREEPDK45=$(CSE148_TOOLS)/FreePDK45 \
-		OPENRAM_HOME=$(CSE148_TOOLS)/OpenRAM-1.2.45/compiler \
-		OPENRAM_TECH=$(CSE148_TOOLS)/OpenRAM-1.2.45/technology \
-		   python3 $(CSE148_TOOLS)/OpenRAM-1.2.45/sram_compiler.py config
+		OPENRAM_HOME=$(CSE148_TOOLS)/$(open_RAM)/compiler \
+		OPENRAM_TECH=$(CSE148_TOOLS)/$(open_RAM)/technology \
+		   python3 $(CSE148_TOOLS)/$(open_RAM)/sram_compiler.py config
 
 netlist.v: mips_core.v $(ram_targets) synthesis.ys
 	bash -c "source $(CSE148_TOOLS)/oss-cad-suite/environment && yosys -s synthesis.ys -l synthesis.log -t"