From 825e38c4a22b43f8f8711f34d865fc56a582d487 Mon Sep 17 00:00:00 2001
From: spramesh2123 <spramesh@ucsd.edu>
Date: Tue, 4 Apr 2023 21:25:16 -0700
Subject: [PATCH]  updating comments

---
 mips_cpu/mips_core/d_cache.sv | 9 ++++++---
 mips_cpu/mips_core/i_cache.sv | 7 ++++---
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/mips_cpu/mips_core/d_cache.sv b/mips_cpu/mips_core/d_cache.sv
index 282daea..6cdbc34 100644
--- a/mips_cpu/mips_core/d_cache.sv
+++ b/mips_cpu/mips_core/d_cache.sv
@@ -1,13 +1,16 @@
 /*
  * d_cache.sv
  * Author: Zinsser Zhang
- * Last Revision: 03/13/2022
+ * Revision : Sankara 			
+ * Last Revision: 04/04/2023
  *
- * This is a direct-mapped data cache. Line size and depth (number of lines) are
+ * This is a 2-way set associative data cache. Line size and depth (number of lines) are
  * set via INDEX_WIDTH and BLOCK_OFFSET_WIDTH parameters. Notice that line size
  * means number of words (each consist of 32 bit) in a line. Because all
  * addresses in mips_core are 26 byte addresses, so the sum of TAG_WIDTH,
  * INDEX_WIDTH and BLOCK_OFFSET_WIDTH is `ADDR_WIDTH - 2.
+ * The ASSOCIATIVITY is fixed at 2 because of the replacement policy. The replacement
+ * policy also needs changes when changing the ASSOCIATIVITY 
  *
  * Typical line sizes are from 2 words to 8 words. The memory interfaces only
  * support up to 8 words line size.
@@ -36,7 +39,7 @@ interface d_cache_input_ifc ();
 endinterface
 
 module d_cache #(
-	parameter INDEX_WIDTH = 6,
+	parameter INDEX_WIDTH = 6,  // 2 * 1 KB Cache Size 
 	parameter BLOCK_OFFSET_WIDTH = 2,
 	parameter ASSOCIATIVITY = 2
 	)(
diff --git a/mips_cpu/mips_core/i_cache.sv b/mips_cpu/mips_core/i_cache.sv
index 4039cb5..9b8fe3f 100644
--- a/mips_cpu/mips_core/i_cache.sv
+++ b/mips_cpu/mips_core/i_cache.sv
@@ -1,7 +1,8 @@
 /*
  * i_cache.sv
- * Author: Zinsser Zhang
- * Last Revision: 03/13/2022
+ * Author: Zinsser Zhang 
+ * Revision : Sankara 			
+ * Last Revision: 04/04/2023
  *
  * This is a direct-mapped instruction cache. Line size and depth (number of
  * lines) are set via INDEX_WIDTH and BLOCK_OFFSET_WIDTH parameters. Notice that
@@ -25,7 +26,7 @@
 `include "mips_core.svh"
 
 module i_cache #(
-	parameter INDEX_WIDTH = 6,
+	parameter INDEX_WIDTH = 6, // 1 KB Cahe size 
 	parameter BLOCK_OFFSET_WIDTH = 2
 	)(
 	// General signals
-- 
1.9.1