automata.kicad_pcb
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(kicad_pcb (version 3) (host pcbnew "(2013-may-18)-stable")
(general
(links 21)
(no_connects 18)
(area 0 0 0 0)
(thickness 1.6)
(drawings 1)
(tracks 8)
(zones 0)
(modules 6)
(nets 20)
)
(page A3)
(layers
(15 F.Cu signal)
(0 B.Cu signal)
(16 B.Adhes user)
(17 F.Adhes user)
(18 B.Paste user)
(19 F.Paste user)
(20 B.SilkS user)
(21 F.SilkS user)
(22 B.Mask user)
(23 F.Mask user)
(24 Dwgs.User user)
(25 Cmts.User user)
(26 Eco1.User user)
(27 Eco2.User user)
(28 Edge.Cuts user)
)
(setup
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(trace_clearance 0.254)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.254)
(segment_width 0.2)
(edge_width 0.1)
(via_size 0.889)
(via_drill 0.635)
(via_min_size 0.889)
(via_min_drill 0.508)
(uvia_size 0.508)
(uvia_drill 0.127)
(uvias_allowed no)
(uvia_min_size 0.508)
(uvia_min_drill 0.127)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.5 1.5)
(pad_drill 0.6)
(pad_to_mask_clearance 0)
(aux_axis_origin 0 0)
(visible_elements FFFFFFBF)
(pcbplotparams
(layerselection 3178497)
(usegerberextensions true)
(excludeedgelayer true)
(linewidth 0.150000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotothertext true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 /P1.0)
(net 2 /P1.1)
(net 3 /P1.2)
(net 4 /P1.3)
(net 5 /P1.4)
(net 6 /P1.5)
(net 7 /P1.6)
(net 8 /P1.7)
(net 9 /P2.0)
(net 10 /P2.1)
(net 11 /P2.2)
(net 12 /P2.3)
(net 13 /P2.4)
(net 14 /P2.5)
(net 15 /P2.6)
(net 16 /P2.7)
(net 17 /RST)
(net 18 GND)
(net 19 VCC)
(net_class Default "This is the default net class."
(clearance 0.254)
(trace_width 0.254)
(via_dia 0.889)
(via_drill 0.635)
(uvia_dia 0.508)
(uvia_drill 0.127)
(add_net "")
(add_net /P1.0)
(add_net /P1.1)
(add_net /P1.2)
(add_net /P1.3)
(add_net /P1.4)
(add_net /P1.5)
(add_net /P1.6)
(add_net /P1.7)
(add_net /P2.0)
(add_net /P2.1)
(add_net /P2.2)
(add_net /P2.3)
(add_net /P2.4)
(add_net /P2.5)
(add_net /P2.6)
(add_net /P2.7)
(add_net /RST)
(add_net GND)
(add_net VCC)
)
(module SM1206 (layer F.Cu) (tedit 42806E24) (tstamp 534C7D23)
(at 218.44 121.92)
(path /534C7525)
(attr smd)
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)
(fp_text value 47k (at 0 0) (layer F.SilkS) hide
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(pad 1 smd rect (at -1.651 0) (size 1.524 2.032)
(layers F.Cu F.Paste F.Mask)
(net 19 VCC)
)
(pad 2 smd rect (at 1.651 0) (size 1.524 2.032)
(layers F.Cu F.Paste F.Mask)
(net 17 /RST)
)
(model smd/chip_cms.wrl
(at (xyz 0 0 0))
(scale (xyz 0.17 0.16 0.16))
(rotate (xyz 0 0 0))
)
)
(module SM1206 (layer F.Cu) (tedit 42806E24) (tstamp 534C79DE)
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(path /534C7858)
(attr smd)
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(pad 1 smd rect (at -1.651 0 90) (size 1.524 2.032)
(layers F.Cu F.Paste F.Mask)
(net 19 VCC)
)
(pad 2 smd rect (at 1.651 0 90) (size 1.524 2.032)
(layers F.Cu F.Paste F.Mask)
(net 18 GND)
)
(model smd/chip_cms.wrl
(at (xyz 0 0 0))
(scale (xyz 0.17 0.16 0.16))
(rotate (xyz 0 0 0))
)
)
(module DIP-20__300 (layer F.Cu) (tedit 200000) (tstamp 534C7A4E)
(at 234.95 128.27)
(descr "20 pins DIL package, round pads")
(tags DIL)
(path /52DC27FD)
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(net 19 VCC)
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(net 1 /P1.0)
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)
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)
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)
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(net 12 /P2.3)
)
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(layers *.Cu *.Mask F.SilkS)
(net 13 /P2.4)
)
(pad 13 thru_hole circle (at 6.35 -3.81) (size 1.397 1.397) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 14 /P2.5)
)
(pad 14 thru_hole circle (at 3.81 -3.81) (size 1.397 1.397) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 7 /P1.6)
)
(pad 15 thru_hole circle (at 1.27 -3.81) (size 1.397 1.397) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 8 /P1.7)
)
(pad 16 thru_hole circle (at -1.27 -3.81) (size 1.397 1.397) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 17 /RST)
)
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(layers *.Cu *.Mask F.SilkS)
)
(pad 18 thru_hole circle (at -6.35 -3.81) (size 1.397 1.397) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 16 /P2.7)
)
(pad 19 thru_hole circle (at -8.89 -3.81) (size 1.397 1.397) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 15 /P2.6)
)
(pad 20 thru_hole circle (at -11.43 -3.81) (size 1.397 1.397) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 18 GND)
)
(model dil/dil_20.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module TO92-123 (layer F.Cu) (tedit 4C5F51CE) (tstamp 534C839A)
(at 218.44 135.89 90)
(descr "Transistor TO92 brochage type BC237")
(tags "TR TO92")
(path /534C765B)
(fp_text reference Q1 (at -1.27 3.81 90) (layer F.SilkS)
(effects (font (size 1.016 1.016) (thickness 0.2032)))
)
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)
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)
(model discret/to98.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
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)
)
(module SIL-8 (layer F.Cu) (tedit 200000) (tstamp 534C8854)
(at 234.95 139.7)
(descr "Connecteur 8 pins")
(tags "CONN DEV")
(path /534C8646)
(fp_text reference P1 (at -6.35 -2.54) (layer F.SilkS)
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)
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)
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)
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)
)
(module SIL-8 (layer F.Cu) (tedit 200000) (tstamp 534C89DD)
(at 234.95 116.84 180)
(descr "Connecteur 8 pins")
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