Venkataram Edavamadathil Sivaram / supermips

Commit 0da65f785c675395c17c662413448f89f4147886

Authored by zinsser 2018-04-13 00:02:10 -0700

Exists in master and in 5 other branches

Add fast simulation files.

Showing 9 changed files with 480 additions and 22 deletions Inline Diff

README.md
mips_cpu/fast_sdram.sv
mips_cpu/fast_testbench.do
mips_cpu/fast_testbench.sv
mips_cpu/fast_wave.do
mips_cpu/mips_core/decoder.sv
mips_cpu/mips_core/glue_circuits.sv
mips_cpu/testbench.sv
mips_cpu/wave.do

#CSE 148 Baseline version 2.1	1	1	# CSE 148 Baseline version 2.2
##Release v2.1 04/10/2018 Zinsser Zhang	2	2
		3	## Release v2.2 04/12/2018 Zinsser Zhang
	3	4
Please refer to the wiki page Walkthrough for instructions to play around the design really quick.	4	5	Please refer to the wiki page Walkthrough for instructions to play around the design really quick.
Detailed documentations can be found in the wiki of this repository.	5	6	Detailed documentations can be found in the wiki of this repository.
	6	7

File was created	1	/*
	2	* fast_sdram.sv
	3	* Author: Zinsser Zhang
	4	* Last Revision: 04/12/2018
	5	*
	6	* This is a fast sdram simulation model. It is fast in terms of simulation
	7	* speed. This module should only be used to verify the functionality of your
	8	* design. And it is not guaranteed that your design can pass the full
	9	* simulation if it passes the fast simulation. You still need to run the full
	10	* simulation to make sure everything works. Performance measurement should also
	11	* be done with the full simulation.
	12	*
	13	* See wiki page "Speed up Simulation" for details.
	14	*/
	15	`timescale 1ns / 1ps
	16	`include "mips_cpu.svh"
	17
	18	module fast_sdram #(parameter DELAY = 20)(
	19	// General signals
	20	input clk, // Clock
	21	input rst_n, // Asynchronous reset active low
	22
	23	// Memory interfaces
	24	mem_read_ifc.response i_cache_read,
	25	mem_write_ifc.response d_cache_write,
	26	mem_read_ifc.response d_cache_read
	27	);
	28
	29	logic [`DATA_WIDTH - 1 : 0] mem [1 << (`ADDR_WIDTH - 2)];
	30
	31	logic rst;
	32	assign rst = ~rst_n;
	33
	34	logic odd_cycle;
	35
	36	enum {
	37	STATE_IDLE,
	38	STATE_DELAY,
	39	STATE_SERVE_IREAD,
	40	STATE_SERVE_DREAD,
	41	STATE_SERVE_DWRITE
	42	} state, next_state;
	43
	44	integer delay_counter;
	45	logic ir_pending, dr_pending, dw_pending;
	46
	47	assign i_cache_read.control_done = ~ir_pending;
	48	assign d_cache_read.control_done = ~dr_pending;
	49	assign d_cache_write.control_done = ~dw_pending;
	50
	51	logic [`ADDR_WIDTH - 1 : 0] pointer, pending_length;
	52	logic [`ADDR_WIDTH - 1 : 0] ir_base, ir_length;
	53	logic [`ADDR_WIDTH - 1 : 0] dr_base, dr_length;
	54	logic [`ADDR_WIDTH - 1 : 0] dw_base, dw_length;
	55
	56
	57	logic [`DATA_WIDTH - 1 : 0] iread_data, dread_data, dwrite_data;
	58	logic iread_empty, iread_full, iread_we;
	59	logic dread_empty, dread_full, dread_we;
	60	logic dwrite_empty, dwrite_full, dwrite_re;
	61
	62	assign iread_data = mem[pointer[2 +: `ADDR_WIDTH - 2]];
	63	assign dread_data = mem[pointer[2 +: `ADDR_WIDTH - 2]];
	64
	65	assign i_cache_read.user_available = ~iread_empty;
	66	scfifo iread_fifo (
	67	.aclr (rst),
	68	.clock (clk),
	69	.empty (iread_empty),
	70	.full (iread_full),
	71	.data (iread_data),
	72	.q (i_cache_read.user_data),
	73	.rdreq (i_cache_read.user_re),
	74	.wrreq (iread_we)
	75	);
	76	defparam iread_fifo.add_ram_output_register = "OFF",
	77	iread_fifo.intended_device_family = "Cyclone V",
	78	iread_fifo.lpm_numwords = 32,
	79	iread_fifo.lpm_showahead = "ON",
	80	iread_fifo.lpm_type = "scfifo",
	81	iread_fifo.lpm_width = `DATA_WIDTH,
	82	iread_fifo.lpm_widthu = 5,
	83	iread_fifo.overflow_checking = "OFF",
	84	iread_fifo.underflow_checking = "OFF",
	85	iread_fifo.use_eab = "ON";
	86
	87	assign d_cache_read.user_available = ~dread_empty;
	88	scfifo dread_fifo (
	89	.aclr (rst),
	90	.clock (clk),
	91	.empty (dread_empty),
	92	.full (dread_full),
	93	.data (dread_data),
	94	.q (d_cache_read.user_data),
	95	.rdreq (d_cache_read.user_re),
	96	.wrreq (dread_we)
	97	);
	98	defparam dread_fifo.add_ram_output_register = "OFF",
	99	dread_fifo.intended_device_family = "Cyclone V",
	100	dread_fifo.lpm_numwords = 32,
	101	dread_fifo.lpm_showahead = "ON",
	102	dread_fifo.lpm_type = "scfifo",
	103	dread_fifo.lpm_width = `DATA_WIDTH,
	104	dread_fifo.lpm_widthu = 5,
	105	dread_fifo.overflow_checking = "OFF",
	106	dread_fifo.underflow_checking = "OFF",
	107	dread_fifo.use_eab = "ON";
	108
	109	assign d_cache_write.user_full = dwrite_full;
	110	scfifo dwrite_fifo (
	111	.aclr (rst),
	112	.clock (clk),
	113	.empty (dwrite_empty),
	114	.full (dwrite_full),
	115	.data (d_cache_write.user_data),
	116	.q (dwrite_data),
	117	.rdreq (dwrite_re),
	118	.wrreq (d_cache_write.user_we)
	119	);
	120	defparam dwrite_fifo.add_ram_output_register = "OFF",
	121	dwrite_fifo.intended_device_family = "Cyclone V",
	122	dwrite_fifo.lpm_numwords = 32,
	123	dwrite_fifo.lpm_showahead = "ON",
	124	dwrite_fifo.lpm_type = "scfifo",
	125	dwrite_fifo.lpm_width = `DATA_WIDTH,
	126	dwrite_fifo.lpm_widthu = 5,
	127	dwrite_fifo.overflow_checking = "OFF",
	128	dwrite_fifo.underflow_checking = "OFF",
	129	dwrite_fifo.use_eab = "ON";
	130
	131	assign iread_we = (state == STATE_SERVE_IREAD ) && (pending_length != '0) && !iread_full && odd_cycle;
	132	assign dread_we = (state == STATE_SERVE_DREAD ) && (pending_length != '0) && !dread_full && ~odd_cycle;
	133	assign dwrite_re = (state == STATE_SERVE_DWRITE) && (pending_length != '0) && !dwrite_empty;
	134
	135	always_comb
	136	begin
	137	next_state <= state;
	138
	139	case (state)
	140	STATE_IDLE:
	141	begin
	142	if (ir_pending \| dr_pending \| dw_pending)
	143	next_state <= STATE_DELAY;
	144	end
	145
	146	STATE_DELAY:
	147	begin
	148	if (delay_counter == 0)
	149	begin
	150	if (ir_pending) next_state <= STATE_SERVE_IREAD;
	151	else if (dr_pending) next_state <= STATE_SERVE_DREAD;
	152	else if (dw_pending) next_state <= STATE_SERVE_DWRITE;
	153	end
	154	end
	155
	156	default: if (pending_length == '0) next_state <= STATE_IDLE;
	157	endcase
	158	end
	159
	160
	161	always_ff @(posedge clk or negedge rst_n)
	162	begin
	163	if(~rst_n)
	164	begin
	165	state <= STATE_IDLE;
	166	delay_counter <= 0;
	167	pending_length <= '0;
	168	ir_pending <= 1'b0;
	169	dr_pending <= 1'b0;
	170	dw_pending <= 1'b0;
	171	odd_cycle <= 1'b0;
	172	end
	173	else
	174	begin
	175	odd_cycle <= ~odd_cycle;
	176	state <= next_state;
	177	if (i_cache_read.control_go)
	178	begin
	179	ir_pending <= 1'b1;
	180	ir_base <= i_cache_read.control_base;
	181	ir_length <= i_cache_read.control_length;
	182	end
	183
	184	if (d_cache_read.control_go)
	185	begin
	186	dr_pending <= 1'b1;
	187	dr_base <= d_cache_read.control_base;
	188	dr_length <= d_cache_read.control_length;
	189	end
	190
	191	if (d_cache_write.control_go)
	192	begin
	193	dw_pending <= 1'b1;
	194	dw_base <= d_cache_write.control_base;
	195	dw_length <= d_cache_write.control_length;
	196	end
	197
	198	case (state)
	199	STATE_IDLE:
	200	begin
	201	if (next_state == STATE_DELAY)
	202	delay_counter <= DELAY;
	203	end
	204
	205	STATE_DELAY:
	206	begin
	207	if (delay_counter > 0)
	208	delay_counter <= delay_counter - 1;
	209	else
	210	begin
	211	if (next_state == STATE_SERVE_IREAD)
	212	begin
	213	pointer <= ir_base;
	214	pending_length <= ir_length;
	215	end
	216	else if (next_state == STATE_SERVE_DREAD)
	217	begin
	218	pointer <= dr_base;
	219	pending_length <= dr_length;
	220	end
	221	else if (next_state == STATE_SERVE_DWRITE)
	222	begin
	223	pointer <= dw_base;
	224	pending_length <= dw_length;
	225	end
	226	end
	227	end
	228
	229	STATE_SERVE_IREAD:
	230	begin
	231	if (next_state == STATE_IDLE) ir_pending <= 1'b0;
	232	else if (iread_we)
	233	begin

File was created	1	# fast_testbench.do
	2	# Author: Zinsser Zhang
	3	# Last Revision: 04/12/2018
	4
	5	# Compile the testbench
	6	vlog -reportprogress 300 -work work ../../fast_testbench.sv
	7
	8	# Compile the simulation model of sdram
	9	vlog -reportprogress 300 -work work ../../fast_sdram.sv

File was created	1	/*
	2	* fast_testbench.sv
	3	* Author: Zinsser Zhang
	4	* Last Revision: 04/12/2018
	5	*
	6	* This is a fast simulation testbench. It is fast in terms of simulation
	7	* speed. This module should only be used to verify the functionality of your
	8	* design. And it is not guaranteed that your design can pass the full
	9	* simulation if it passes the fast simulation. You still need to run the full
	10	* simulation to make sure everything works. Performance measurement should also
	11	* be done with the full simulation.
	12	*
	13	* See wiki page "Speed up Simulation" for details.
	14	*/
	15	`timescale 1 ns / 1 ps
	16	`include "mips_cpu.svh"
	17
	18	module fast_testbench ();
	19
	20	logic clk, rst_n;
	21	mem_read_ifc i_cache_read();
	22	mem_write_ifc d_cache_write();
	23	mem_read_ifc d_cache_read();
	24
	25	pass_done_ifc pass_done();
	26
	27
	28	mips_core MIPS_CORE (
	29	.clk, .rst_n,
	30
	31	.i_cache_read,
	32	.d_cache_write,
	33	.d_cache_read,
	34
	35	.pass_done
	36	);
	37
	38	fast_sdram FAST_SDRAM (
	39	.clk, .rst_n,
	40
	41	.i_cache_read,
	42	.d_cache_write,
	43	.d_cache_read
	44	);
	45	defparam FAST_SDRAM.DELAY = 20;
	46
	47	// Generate reference clock
	48	always
	49	begin
	50	#5 clk = ~clk;
	51	end
	52
	53	initial
	54	begin
	55	clk = 1'b0;
	56	rst_n = 1'b0;
	57
	58	repeat (10) @(posedge clk); // Wait for 10 cycles
	59	rst_n = 1'b1; // Release reset
	60

File was created	1	onerror {resume}
	2	quietly WaveActivateNextPane {} 0
	3	add wave -noupdate -divider {IF Stage}
	4	add wave -noupdate /fast_testbench/MIPS_CORE/clk
	5	add wave -noupdate /fast_testbench/MIPS_CORE/rst_n
	6	add wave -noupdate /fast_testbench/MIPS_CORE/i2i_hc/stall
	7	add wave -noupdate -color {Slate Blue} -radix hexadecimal /fast_testbench/MIPS_CORE/if_pc_current/pc
	8	add wave -noupdate -color {Slate Blue} -radix hexadecimal /fast_testbench/MIPS_CORE/if_pc_next/pc
	9	add wave -noupdate /fast_testbench/MIPS_CORE/if_i_cache_output/valid
	10	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/if_i_cache_output/data
	11	add wave -noupdate -divider {IF to DEC}
	12	add wave -noupdate /fast_testbench/MIPS_CORE/i2d_hc/flush
	13	add wave -noupdate /fast_testbench/MIPS_CORE/i2d_hc/stall
	14	add wave -noupdate -divider {DEC Stage}
	15	add wave -noupdate /fast_testbench/MIPS_CORE/clk
	16	add wave -noupdate -color {Slate Blue} -radix hexadecimal /fast_testbench/MIPS_CORE/i2d_pc/pc
	17	add wave -noupdate /fast_testbench/MIPS_CORE/i2d_inst/valid
	18	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/i2d_inst/data
	19	add wave -noupdate -divider <NULL>
	20	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/valid
	21	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/alu_ctl
	22	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/is_branch_jump
	23	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/is_jump
	24	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/is_jump_reg
	25	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/dec_decoder_output/branch_target
	26	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/is_mem_access
	27	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/mem_action
	28	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/uses_rs
	29	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/rs_addr
	30	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/uses_rt
	31	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/rt_addr
	32	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/uses_immediate
	33	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/dec_decoder_output/immediate
	34	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/uses_rw
	35	add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/rw_addr
	36	add wave -noupdate -divider <NULL>
	37	add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/valid
	38	add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/is_jump
	39	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/target
	40	add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/prediction
	41	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/recovery_target
	42	add wave -noupdate -divider <NULL>
	43	add wave -noupdate -color Cyan -radix hexadecimal -childformat {{{/fast_testbench/MIPS_CORE/REG_FILE/regs[0]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[1]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[2]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[3]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[4]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[5]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[6]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[7]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[8]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[9]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[10]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[11]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[12]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[13]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[14]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[15]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[16]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[17]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[18]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[19]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[20]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[21]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[22]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[23]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[24]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[25]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[26]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[27]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[28]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[29]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[30]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[31]} -radix hexadecimal}} -expand -subitemconfig {{/fast_testbench/MIPS_CORE/REG_FILE/regs[0]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[1]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[2]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[3]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[4]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[5]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[6]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[7]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[8]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[9]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[10]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[11]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[12]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[13]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[14]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[15]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[16]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[17]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[18]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[19]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[20]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[21]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[22]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[23]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[24]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[25]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[26]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[27]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[28]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[29]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[30]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[31]} {-color Cyan -radix hexadecimal}} /fast_testbench/MIPS_CORE/REG_FILE/regs
	44	add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/o_alu_input/valid
	45	add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/o_alu_input/alu_ctl
	46	add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/o_alu_input/op1
	47	add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/o_alu_input/op2
	48	add wave -noupdate -divider {DEC to EX}
	49	add wave -noupdate /fast_testbench/MIPS_CORE/d2e_hc/flush
	50	add wave -noupdate /fast_testbench/MIPS_CORE/d2e_hc/stall
	51	add wave -noupdate -divider {EX Stage}
	52	add wave -noupdate /fast_testbench/MIPS_CORE/clk
	53	add wave -noupdate -color {Slate Blue} -radix hexadecimal /fast_testbench/MIPS_CORE/d2e_pc/pc
	54	add wave -noupdate /fast_testbench/MIPS_CORE/ex_alu_output/valid
	55	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/ex_alu_output/result
	56	add wave -noupdate /fast_testbench/MIPS_CORE/ex_alu_output/branch_outcome
	57	add wave -noupdate -divider <NULL>
	58	add wave -noupdate /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/valid
	59	add wave -noupdate /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/prediction
	60	add wave -noupdate /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/outcome
	61	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/recovery_target
	62	add wave -noupdate /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/valid
	63	add wave -noupdate /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/mem_action
	64	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/addr
	65	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/addr_next
	66	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/data
	67	add wave -noupdate -divider {EX to MEM}
	68	add wave -noupdate /fast_testbench/MIPS_CORE/e2m_hc/flush
	69	add wave -noupdate /fast_testbench/MIPS_CORE/e2m_hc/stall
	70	add wave -noupdate -divider {MEM Stage}
	71	add wave -noupdate /fast_testbench/MIPS_CORE/clk
	72	add wave -noupdate -color {Slate Blue} -radix hexadecimal /fast_testbench/MIPS_CORE/e2m_pc/pc
	73	add wave -noupdate /fast_testbench/MIPS_CORE/mem_d_cache_output/valid
	74	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/mem_d_cache_output/data
	75	add wave -noupdate -divider {MEM to WB}
	76	add wave -noupdate /fast_testbench/MIPS_CORE/m2w_hc/flush
	77	add wave -noupdate /fast_testbench/MIPS_CORE/m2w_hc/stall
	78	add wave -noupdate -divider {WB Stage}
	79	add wave -noupdate /fast_testbench/MIPS_CORE/clk
	80	add wave -noupdate /fast_testbench/MIPS_CORE/m2w_write_back/uses_rw
	81	add wave -noupdate /fast_testbench/MIPS_CORE/m2w_write_back/rw_addr
	82	add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/m2w_write_back/rw_data
	83	add wave -noupdate -divider Hazards
	84	add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/lw_hazard
	85	add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/ic_miss
	86	add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/ds_miss
	87	add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/dec_overload
	88	add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/ex_overload
	89	add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/dc_miss
	90	TreeUpdate [SetDefaultTree]
	91	WaveRestoreCursors {{Cursor 1} {36408825 ps} 0}
	92	quietly wave cursor active 1
	93	configure wave -namecolwidth 386
	94	configure wave -valuecolwidth 100
	95	configure wave -justifyvalue left
	96	configure wave -signalnamewidth 0
	97	configure wave -snapdistance 10
	98	configure wave -datasetprefix 0
	99	configure wave -rowmargin 4
	100	configure wave -childrowmargin 2
	101	configure wave -gridoffset 0
	102	configure wave -gridperiod 1
	103	configure wave -griddelta 40
	104	configure wave -timeline 0
	105	configure wave -timelineunits ns
	106	update
	107	WaveRestoreZoom {3531792904 ps} {3531863532 ps}

/*	1	1	/*
* decoder.sv	2	2	* decoder.sv
* Author: Zinsser Zhang	3	3	* Author: Zinsser Zhang
* Last Revision: 04/08/2018	4	4	* Last Revision: 04/08/2018
*	5	5	*
* Decoder decode an instruction to control signals.	6	6	* Decoder decode an instruction to control signals.
*	7	7	*
* See wiki page "Branch and Jump" for details about branch/jump instructions.	8	8	* See wiki page "Branch and Jump" for details about branch/jump instructions.
* See wiki page "Handle Register Zero" for deatils about instructions reading	9	9	* See wiki page "Handle Register Zero" for deatils about instructions reading
* from or writing to register zero.	10	10	* from or writing to register zero.
*/	11	11	*/
`include "mips_core.svh"	12	12	`include "mips_core.svh"
	13	13
interface decoder_output_ifc ();	14	14	interface decoder_output_ifc ();
logic valid;	15	15	logic valid;
mips_core_pkg::AluCtl alu_ctl;	16	16	mips_core_pkg::AluCtl alu_ctl;
logic is_branch;	17	17	logic is_branch_jump;
logic is_jump;	18	18	logic is_jump;
logic is_jump_reg;	19	19	logic is_jump_reg;
logic [`ADDR_WIDTH - 1 : 0] branch_target;	20	20	logic [`ADDR_WIDTH - 1 : 0] branch_target;
	21	21
logic is_mem_access;	22	22	logic is_mem_access;
mips_core_pkg::MemAccessType mem_action;	23	23	mips_core_pkg::MemAccessType mem_action;
	24	24
logic uses_rs;	25	25	logic uses_rs;
mips_core_pkg::MipsReg rs_addr;	26	26	mips_core_pkg::MipsReg rs_addr;
	27	27
logic uses_rt;	28	28	logic uses_rt;
mips_core_pkg::MipsReg rt_addr;	29	29	mips_core_pkg::MipsReg rt_addr;
	30	30
logic uses_immediate;	31	31	logic uses_immediate;
logic [`DATA_WIDTH - 1 : 0] immediate;	32	32	logic [`DATA_WIDTH - 1 : 0] immediate;
	33	33
logic uses_rw;	34	34	logic uses_rw;
mips_core_pkg::MipsReg rw_addr;	35	35	mips_core_pkg::MipsReg rw_addr;
	36	36
modport in (input valid, alu_ctl, is_branch, is_jump, is_jump_reg,	37	37	modport in (input valid, alu_ctl, is_branch_jump, is_jump, is_jump_reg,
branch_target, is_mem_access, mem_action, uses_rs, rs_addr, uses_rt,	38	38	branch_target, is_mem_access, mem_action, uses_rs, rs_addr, uses_rt,
rt_addr, uses_immediate, immediate, uses_rw, rw_addr);	39	39	rt_addr, uses_immediate, immediate, uses_rw, rw_addr);
modport out (output valid, alu_ctl, is_branch, is_jump, is_jump_reg,	40	40	modport out (output valid, alu_ctl, is_branch_jump, is_jump, is_jump_reg,
branch_target, is_mem_access, mem_action, uses_rs, rs_addr, uses_rt,	41	41	branch_target, is_mem_access, mem_action, uses_rs, rs_addr, uses_rt,
rt_addr, uses_immediate, immediate, uses_rw, rw_addr);	42	42	rt_addr, uses_immediate, immediate, uses_rw, rw_addr);
endinterface	43	43	endinterface
	44	44
module decoder (	45	45	module decoder (
pc_ifc.in i_pc,	46	46	pc_ifc.in i_pc,
cache_output_ifc.in i_inst,	47	47	cache_output_ifc.in i_inst,
	48	48
decoder_output_ifc.out out	49	49	decoder_output_ifc.out out
);	50	50	);
	51	51
task uses_rs;	52	52	task uses_rs;
begin	53	53	begin
// Only set uses_rs if it is not register zero	54	54	// Only set uses_rs if it is not register zero
out.uses_rs <= \|i_inst.data[25:21];	55	55	out.uses_rs <= \|i_inst.data[25:21];
out.rs_addr <= mips_core_pkg::MipsReg'(i_inst.data[25:21]);	56	56	out.rs_addr <= mips_core_pkg::MipsReg'(i_inst.data[25:21]);
end	57	57	end
endtask	58	58	endtask
	59	59
task uses_rt;	60	60	task uses_rt;
begin	61	61	begin
// Only set uses_rt if it is not register zero	62	62	// Only set uses_rt if it is not register zero
out.uses_rt <= \|i_inst.data[20:16];	63	63	out.uses_rt <= \|i_inst.data[20:16];
out.rt_addr <= mips_core_pkg::MipsReg'(i_inst.data[20:16]);	64	64	out.rt_addr <= mips_core_pkg::MipsReg'(i_inst.data[20:16]);
end	65	65	end
endtask	66	66	endtask
	67	67
task route_rt_to_rs;	68	68	task route_rt_to_rs;
begin	69	69	begin
// Rerouting rt to rs for sll, srl, sra	70	70	// Rerouting rt to rs for sll, srl, sra
// Only set uses_rs if it is not register zero	71	71	// Only set uses_rs if it is not register zero
out.uses_rs <= \|i_inst.data[20:16];	72	72	out.uses_rs <= \|i_inst.data[20:16];
out.rs_addr <= mips_core_pkg::MipsReg'(i_inst.data[20:16]);	73	73	out.rs_addr <= mips_core_pkg::MipsReg'(i_inst.data[20:16]);
end	74	74	end
endtask	75	75	endtask
	76	76
task uses_immediate_raw;	77	77	task uses_immediate_raw;
input [31:0] immediate;	78	78	input [31:0] immediate;
begin	79	79	begin
out.uses_immediate <= 1'b1;	80	80	out.uses_immediate <= 1'b1;
out.immediate <= immediate;	81	81	out.immediate <= immediate;
end	82	82	end
endtask	83	83	endtask
	84	84
task uses_immediate_zero_extend;	85	85	task uses_immediate_zero_extend;
uses_immediate_raw(32'(unsigned'(i_inst.data[15:0])));	86	86	uses_immediate_raw(32'(unsigned'(i_inst.data[15:0])));
endtask	87	87	endtask
	88	88
task uses_immediate_signed_extend;	89	89	task uses_immediate_signed_extend;
uses_immediate_raw(32'(signed'(i_inst.data[15:0])));	90	90	uses_immediate_raw(32'(signed'(i_inst.data[15:0])));
endtask	91	91	endtask
	92	92
task uses_immediate_shamt;	93	93	task uses_immediate_shamt;
uses_immediate_raw(32'(unsigned'(i_inst.data[10:6])));	94	94	uses_immediate_raw(32'(unsigned'(i_inst.data[10:6])));
endtask	95	95	endtask
	96	96
task uses_rw_raw;	97	97	task uses_rw_raw;
input [4:0] rw;	98	98	input [4:0] rw;
begin	99	99	begin
// Only set uses_rw if it is not register zero	100	100	// Only set uses_rw if it is not register zero
out.uses_rw <= \|rw;	101	101	out.uses_rw <= \|rw;
out.rw_addr <= mips_core_pkg::MipsReg'(rw);	102	102	out.rw_addr <= mips_core_pkg::MipsReg'(rw);
end	103	103	end
endtask	104	104	endtask
	105	105
task uses_rw_rtype;	106	106	task uses_rw_rtype;
uses_rw_raw(i_inst.data[15:11]);	107	107	uses_rw_raw(i_inst.data[15:11]);
endtask	108	108	endtask
	109	109
task uses_rw_itype;	110	110	task uses_rw_itype;
uses_rw_raw(i_inst.data[20:16]);	111	111	uses_rw_raw(i_inst.data[20:16]);
endtask	112	112	endtask
	113	113
task typical_rtype;	114	114	task typical_rtype;
begin	115	115	begin
uses_rs();	116	116	uses_rs();
uses_rt();	117	117	uses_rt();
uses_rw_rtype();	118	118	uses_rw_rtype();
end	119	119	end
endtask	120	120	endtask
	121	121
task shamt_rtype;	122	122	task shamt_rtype;
begin	123	123	begin
route_rt_to_rs();	124	124	route_rt_to_rs();
uses_rw_rtype();	125	125	uses_rw_rtype();
uses_immediate_shamt();	126	126	uses_immediate_shamt();
end	127	127	end
endtask	128	128	endtask
	129	129
task signed_extend_itype;	130	130	task signed_extend_itype;
begin	131	131	begin
uses_rs();	132	132	uses_rs();
uses_rw_itype();	133	133	uses_rw_itype();
uses_immediate_signed_extend();	134	134	uses_immediate_signed_extend();
end	135	135	end
endtask	136	136	endtask
	137	137
task zero_extend_itype;	138	138	task zero_extend_itype;
begin	139	139	begin
uses_rs();	140	140	uses_rs();
uses_rw_itype();	141	141	uses_rw_itype();
uses_immediate_zero_extend();	142	142	uses_immediate_zero_extend();
end	143	143	end
endtask	144	144	endtask
	145	145
	146	146
	147	147
always_comb	148	148	always_comb
begin	149	149	begin
// Set defaults to nop	150	150	// Set defaults to nop
out.valid <= i_inst.valid;	151	151	out.valid <= i_inst.valid;
out.alu_ctl <= ALUCTL_NOP;	152	152	out.alu_ctl <= ALUCTL_NOP;
out.is_branch <= 1'b0;	153	153	out.is_branch_jump <= 1'b0;
out.is_jump <= 1'b0;	154	154	out.is_jump <= 1'b0;
out.is_jump_reg <= 1'b0;	155	155	out.is_jump_reg <= 1'b0;
out.branch_target <= '0;	156	156	out.branch_target <= '0;
out.is_mem_access <= 1'b0;	157	157	out.is_mem_access <= 1'b0;
out.mem_action <= READ;	158	158	out.mem_action <= READ;
	159	159
out.uses_rs <= 1'b0;	160	160	out.uses_rs <= 1'b0;
out.rs_addr <= zero;	161	161	out.rs_addr <= zero;
	162	162
out.uses_rt <= 1'b0;	163	163	out.uses_rt <= 1'b0;
out.rt_addr <= zero;	164	164	out.rt_addr <= zero;
	165	165
out.uses_immediate <= 1'b0;	166	166	out.uses_immediate <= 1'b0;
out.immediate <= '0;	167	167	out.immediate <= '0;
	168	168
out.uses_rw <= 1'b0;	169	169	out.uses_rw <= 1'b0;
out.rw_addr <= zero;	170	170	out.rw_addr <= zero;
	171	171
if (i_inst.valid)	172	172	if (i_inst.valid)
begin	173	173	begin
case(i_inst.data[31:26])	174	174	case(i_inst.data[31:26])
6'h0: //r-type	175	175	6'h0: //r-type
begin	176	176	begin
case (i_inst.data[5:0])	177	177	case (i_inst.data[5:0])
6'h20: // add	178	178	6'h20: // add
begin	179	179	begin
out.alu_ctl <= ALUCTL_ADD;	180	180	out.alu_ctl <= ALUCTL_ADD;
typical_rtype();	181	181	typical_rtype();
end	182	182	end
	183	183
6'h21: // addu	184	184	6'h21: // addu
begin	185	185	begin
out.alu_ctl <= ALUCTL_ADDU;	186	186	out.alu_ctl <= ALUCTL_ADDU;
typical_rtype();	187	187	typical_rtype();
end	188	188	end
	189	189
6'h22: // sub	190	190	6'h22: // sub
begin	191	191	begin
out.alu_ctl <= ALUCTL_SUB;	192	192	out.alu_ctl <= ALUCTL_SUB;
typical_rtype();	193	193	typical_rtype();
end	194	194	end
	195	195
6'h23: // subu	196	196	6'h23: // subu
begin	197	197	begin
out.alu_ctl <= ALUCTL_SUBU;	198	198	out.alu_ctl <= ALUCTL_SUBU;
typical_rtype();	199	199	typical_rtype();
end	200	200	end
	201	201
6'h24: // and	202	202	6'h24: // and
begin	203	203	begin
out.alu_ctl <= ALUCTL_AND;	204	204	out.alu_ctl <= ALUCTL_AND;
typical_rtype();	205	205	typical_rtype();
end	206	206	end
	207	207
6'h25: // or	208	208	6'h25: // or
begin	209	209	begin
out.alu_ctl <= ALUCTL_OR;	210	210	out.alu_ctl <= ALUCTL_OR;
typical_rtype();	211	211	typical_rtype();
end	212	212	end
	213	213
6'h26: // xor	214	214	6'h26: // xor
begin	215	215	begin
out.alu_ctl <= ALUCTL_XOR;	216	216	out.alu_ctl <= ALUCTL_XOR;
typical_rtype();	217	217	typical_rtype();
end	218	218	end
	219	219
6'h27: // nor	220	220	6'h27: // nor
begin	221	221	begin
out.alu_ctl <= ALUCTL_NOR;	222	222	out.alu_ctl <= ALUCTL_NOR;
typical_rtype();	223	223	typical_rtype();
end	224	224	end
	225	225
6'h00: // sll	226	226	6'h00: // sll
begin	227	227	begin
out.alu_ctl <= ALUCTL_SLL;	228	228	out.alu_ctl <= ALUCTL_SLL;
shamt_rtype();	229	229	shamt_rtype();
end	230	230	end
	231	231
6'h02: // srl	232	232	6'h02: // srl
begin	233	233	begin
out.alu_ctl <= ALUCTL_SRL;	234	234	out.alu_ctl <= ALUCTL_SRL;
shamt_rtype();	235	235	shamt_rtype();
end	236	236	end
	237	237
6'h03: // sra	238	238	6'h03: // sra
begin	239	239	begin
out.alu_ctl <= ALUCTL_SRA;	240	240	out.alu_ctl <= ALUCTL_SRA;
shamt_rtype();	241	241	shamt_rtype();
end	242	242	end
	243	243
6'h04: // sllv	244	244	6'h04: // sllv
begin	245	245	begin
out.alu_ctl <= ALUCTL_SLLV;	246	246	out.alu_ctl <= ALUCTL_SLLV;
typical_rtype();	247	247	typical_rtype();
end	248	248	end
	249	249
6'h06: // srlv	250	250	6'h06: // srlv
begin	251	251	begin
out.alu_ctl <= ALUCTL_SRLV;	252	252	out.alu_ctl <= ALUCTL_SRLV;
typical_rtype();	253	253	typical_rtype();
end	254	254	end
	255	255
6'h07: // srav	256	256	6'h07: // srav
begin	257	257	begin
out.alu_ctl <= ALUCTL_SRAV;	258	258	out.alu_ctl <= ALUCTL_SRAV;
typical_rtype();	259	259	typical_rtype();
end	260	260	end
	261	261
6'h2a: // slt	262	262	6'h2a: // slt
begin	263	263	begin
out.alu_ctl <= ALUCTL_SLT;	264	264	out.alu_ctl <= ALUCTL_SLT;
typical_rtype();	265	265	typical_rtype();
end	266	266	end
	267	267
6'h2b: // sltu	268	268	6'h2b: // sltu
begin	269	269	begin
out.alu_ctl <= ALUCTL_SLTU;	270	270	out.alu_ctl <= ALUCTL_SLTU;
typical_rtype();	271	271	typical_rtype();
end	272	272	end
	273	273
6'h08: // jr	274	274	6'h08: // jr
begin	275	275	begin
out.alu_ctl <= ALUCTL_NOP; // jr does not use alu	276	276	out.alu_ctl <= ALUCTL_NOP; // jr does not use alu
uses_rs();	277	277	uses_rs();
out.is_branch <= 1'b1;	278	278	out.is_branch_jump <= 1'b1;
out.is_jump <= 1'b1;	279	279	out.is_jump <= 1'b1;
out.is_jump_reg <= 1'b1;	280	280	out.is_jump_reg <= 1'b1;
end	281	281	end
	282	282
6'h09: //jalr	283	283	6'h09: //jalr
begin	284	284	begin
out.alu_ctl <= ALUCTL_OR;	285	285	out.alu_ctl <= ALUCTL_OR;
uses_rs();	286	286	uses_rs();
uses_rw_raw(ra); // jalr always write to ra (31)	287	287	uses_rw_raw(ra); // jalr always write to ra (31)
uses_immediate_raw(32'(unsigned'(i_pc.pc)) + 8);	288	288	uses_immediate_raw(32'(unsigned'(i_pc.pc)) + 8);
out.is_branch <= 1'b1;	289	289	out.is_branch_jump <= 1'b1;
out.is_jump <= 1'b1;	290	290	out.is_jump <= 1'b1;
out.is_jump_reg <= 1'b1;	291	291	out.is_jump_reg <= 1'b1;
end	292	292	end
	293	293
6'h18: // mul	294	294	6'h18: // mul
begin	295	295	begin
$error("%m (%t) mul not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);	296	296	$error("%m (%t) mul not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);
out.valid <= 1'b0;	297	297	out.valid <= 1'b0;
end	298	298	end
	299	299
6'h19: //mulu	300	300	6'h19: //mulu
begin	301	301	begin
$error("%m (%t) mulu not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);	302	302	$error("%m (%t) mulu not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);
out.valid <= 1'b0;	303	303	out.valid <= 1'b0;
end	304	304	end
	305	305
6'h1a: //div	306	306	6'h1a: //div
begin	307	307	begin
$error("%m (%t) div not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);	308	308	$error("%m (%t) div not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);
out.valid <= 1'b0;	309	309	out.valid <= 1'b0;
end	310	310	end
	311	311
6'h1b: //divu	312	312	6'h1b: //divu
begin	313	313	begin
$error("%m (%t) divu not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);	314	314	$error("%m (%t) divu not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);
out.valid <= 1'b0;	315	315	out.valid <= 1'b0;
end	316	316	end
	317	317
default:	318	318	default:
begin	319	319	begin
$error("%m (%t) unknown R-type funct code %b. Treated as a NOP. PC=0x%x", $time, i_inst.data[5:0], i_pc.pc);	320	320	$error("%m (%t) unknown R-type funct code %b. Treated as a NOP. PC=0x%x", $time, i_inst.data[5:0], i_pc.pc);
out.valid <= 1'b0;	321	321	out.valid <= 1'b0;
end	322	322	end
endcase	323	323	endcase
end	324	324	end
	325	325
6'h08: //addi	326	326	6'h08: //addi
begin	327	327	begin
out.alu_ctl <= ALUCTL_ADD;	328	328	out.alu_ctl <= ALUCTL_ADD;
signed_extend_itype();	329	329	signed_extend_itype();
end	330	330	end
	331	331
6'h09: //addiu	332	332	6'h09: //addiu
begin	333	333	begin
out.alu_ctl <= ALUCTL_ADDU;	334	334	out.alu_ctl <= ALUCTL_ADDU;
signed_extend_itype();	335	335	signed_extend_itype();
end	336	336	end
	337	337
6'h0c: //andi	338	338	6'h0c: //andi
begin	339	339	begin
out.alu_ctl <= ALUCTL_AND;	340	340	out.alu_ctl <= ALUCTL_AND;
zero_extend_itype();	341	341	zero_extend_itype();
end	342	342	end
	343	343
6'h0d: //ori	344	344	6'h0d: //ori
begin	345	345	begin
out.alu_ctl <= ALUCTL_OR;	346	346	out.alu_ctl <= ALUCTL_OR;
zero_extend_itype();	347	347	zero_extend_itype();
end	348	348	end
	349	349
6'h0e: //xori	350	350	6'h0e: //xori
begin	351	351	begin
out.alu_ctl <= ALUCTL_XOR;	352	352	out.alu_ctl <= ALUCTL_XOR;
zero_extend_itype();	353	353	zero_extend_itype();
end	354	354	end
	355	355
6'h0a: //slti	356	356	6'h0a: //slti
begin	357	357	begin
out.alu_ctl <= ALUCTL_SLT;	358	358	out.alu_ctl <= ALUCTL_SLT;
signed_extend_itype();	359	359	signed_extend_itype();
end	360	360	end
	361	361
6'h0b: //sltiu	362	362	6'h0b: //sltiu
begin	363	363	begin
out.alu_ctl <= ALUCTL_SLTU;	364	364	out.alu_ctl <= ALUCTL_SLTU;
signed_extend_itype();	365	365	signed_extend_itype();
end	366	366	end
	367	367
6'h0f: //lui Implemented as 0 \| Immediate	368	368	6'h0f: //lui Implemented as 0 \| Immediate
begin	369	369	begin
out.alu_ctl <= ALUCTL_OR;	370	370	out.alu_ctl <= ALUCTL_OR;
uses_rw_itype();	371	371	uses_rw_itype();
uses_immediate_raw({i_inst.data[15:0], 16'h0000});	372	372	uses_immediate_raw({i_inst.data[15:0], 16'h0000});
end	373	373	end
	374	374
6'h04: //beq	375	375	6'h04: //beq
begin	376	376	begin
out.alu_ctl <= ALUCTL_BEQ;	377	377	out.alu_ctl <= ALUCTL_BEQ;
uses_rs();	378	378	uses_rs();
uses_rt();	379	379	uses_rt();
out.is_branch <= 1'b1;	380	380	out.is_branch_jump <= 1'b1;
out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);	381	381	out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);
end	382	382	end
	383	383
6'h05: //bne	384	384	6'h05: //bne
begin	385	385	begin
out.alu_ctl <= ALUCTL_BNE;	386	386	out.alu_ctl <= ALUCTL_BNE;
uses_rs();	387	387	uses_rs();
uses_rt();	388	388	uses_rt();
out.is_branch <= 1'b1;	389	389	out.is_branch_jump <= 1'b1;
out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);	390	390	out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);
end	391	391	end
	392	392
6'h06: //blez	393	393	6'h06: //blez
begin	394	394	begin
out.alu_ctl <= ALUCTL_BLEZ;	395	395	out.alu_ctl <= ALUCTL_BLEZ;
uses_rs();	396	396	uses_rs();
uses_rt();	397	397	uses_rt();
out.is_branch <= 1'b1;	398	398	out.is_branch_jump <= 1'b1;
out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);	399	399	out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);
end	400	400	end
	401	401
6'h01: //bgez or bltz	402	402	6'h01: //bgez or bltz
begin	403	403	begin
if( i_inst.data[16] )	404	404	if( i_inst.data[16] )
out.alu_ctl <= ALUCTL_BGEZ;	405	405	out.alu_ctl <= ALUCTL_BGEZ;
else	406	406	else
out.alu_ctl <= ALUCTL_BLTZ;	407	407	out.alu_ctl <= ALUCTL_BLTZ;
uses_rs();	408	408	uses_rs();
uses_rt();	409	409	uses_rt();
out.is_branch <= 1'b1;	410	410	out.is_branch_jump <= 1'b1;
out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);	411	411	out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);
end	412	412	end
	413	413
6'h07: //bgtz	414	414	6'h07: //bgtz
begin	415	415	begin
out.alu_ctl <= ALUCTL_BGTZ;	416	416	out.alu_ctl <= ALUCTL_BGTZ;
uses_rs();	417	417	uses_rs();
uses_rt();	418	418	uses_rt();
out.is_branch <= 1'b1;	419	419	out.is_branch_jump <= 1'b1;
out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);	420	420	out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);
end	421	421	end
	422	422
6'h02: // j	423	423	6'h02: // j
begin	424	424	begin
out.alu_ctl <= ALUCTL_NOP; // jr does not use alu	425	425	out.alu_ctl <= ALUCTL_NOP; // jr does not use alu
out.is_branch <= 1'b1;	426	426	out.is_branch_jump <= 1'b1;
out.is_jump <= 1'b1;	427	427	out.is_jump <= 1'b1;
out.branch_target <= {i_inst.data[`ADDR_WIDTH - 3: 0], 2'b00};	428	428	out.branch_target <= {i_inst.data[`ADDR_WIDTH - 3: 0], 2'b00};
end	429	429	end
	430	430
6'h03: // jal	431	431	6'h03: // jal
begin	432	432	begin
out.alu_ctl <= ALUCTL_OR;	433	433	out.alu_ctl <= ALUCTL_OR;
uses_rw_raw(ra); // jal always write to ra (31)	434	434	uses_rw_raw(ra); // jal always write to ra (31)
uses_immediate_raw(32'(unsigned'(i_pc.pc)) + 8);	435	435	uses_immediate_raw(32'(unsigned'(i_pc.pc)) + 8);
out.is_branch <= 1'b1;	436	436	out.is_branch_jump <= 1'b1;
out.is_jump <= 1'b1;	437	437	out.is_jump <= 1'b1;
out.branch_target <= {i_inst.data[`ADDR_WIDTH - 3: 0], 2'b00};	438	438	out.branch_target <= {i_inst.data[`ADDR_WIDTH - 3: 0], 2'b00};
end	439	439	end
	440	440
6'h20: //lb	441	441	6'h20: //lb
begin	442	442	begin
$error("%m (%t) lb not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);	443	443	$error("%m (%t) lb not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);
out.valid <= 1'b0;	444	444	out.valid <= 1'b0;
end	445	445	end
	446	446
6'h24: //lbu	447	447	6'h24: //lbu
begin	448	448	begin
$error("%m (%t) lbu not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);	449	449	$error("%m (%t) lbu not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);
out.valid <= 1'b0;	450	450	out.valid <= 1'b0;
end	451	451	end
	452	452
6'h21: //lh	453	453	6'h21: //lh
begin	454	454	begin
$error("%m (%t) lh not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);	455	455	$error("%m (%t) lh not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);
out.valid <= 1'b0;	456	456	out.valid <= 1'b0;
end	457	457	end
	458	458
6'h25: //lhu	459	459	6'h25: //lhu
begin	460	460	begin
$error("%m (%t) lhu not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);	461	461	$error("%m (%t) lhu not supported. Treated as a NOP. PC=0x%x", $time, i_pc.pc);
out.valid <= 1'b0;	462	462	out.valid <= 1'b0;
end	463	463	end
	464	464
6'h23: //lw	465	465	6'h23: //lw

/*	1	1	/*
* testbench.sv	2	2	* testbench.sv
* Author: Zinsser Zhang	3	3	* Author: Zinsser Zhang
* Last Revision: 04/08/2018	4	4	* Last Revision: 04/08/2018
*	5	5	*
* This is the simulation testbench. It connects mips_cpu to a sdram model, and	6	6	* This is the simulation testbench. It connects mips_cpu to a sdram model, and
* generates top-level input clock and signals.	7	7	* generates top-level input clock and signals.
*/	8	8	*/
`timescale 1 ns / 1 ps	9	9	`timescale 1 ns / 1 ps
`include "mips_cpu.svh"	10	10	`include "mips_cpu.svh"
	11	11
module testbench ();	12	12	module testbench ();
// Connections to mips_cpu	13	13	// Connections to mips_cpu
logic CLOCK_50;	14	14	logic CLOCK_50;
	15	15
logic [12:0] DRAM_ADDR;	16	16	logic [12:0] DRAM_ADDR;
logic [1:0] DRAM_BA;	17	17	logic [1:0] DRAM_BA;
logic DRAM_CAS_N;	18	18	logic DRAM_CAS_N;
logic DRAM_CKE;	19	19	logic DRAM_CKE;
logic DRAM_CLK;	20	20	logic DRAM_CLK;
logic DRAM_CS_N;	21	21	logic DRAM_CS_N;
wire [15:0] DRAM_DQ;	22	22	wire [15:0] DRAM_DQ;
logic DRAM_LDQM;	23	23	logic DRAM_LDQM;
logic DRAM_RAS_N;	24	24	logic DRAM_RAS_N;
logic DRAM_UDQM;	25	25	logic DRAM_UDQM;
logic DRAM_WE_N;	26	26	logic DRAM_WE_N;
	27	27
logic [9:0] SW;	28	28	logic [9:0] SW;
	29	29
mips_cpu DUT (	30	30	mips_cpu DUT (
.CLOCK_50,	31	31	.CLOCK_50,
	32	32
.DRAM_ADDR,	33	33	.DRAM_ADDR,
.DRAM_BA,	34	34	.DRAM_BA,
.DRAM_CAS_N,	35	35	.DRAM_CAS_N,
.DRAM_CKE,	36	36	.DRAM_CKE,
.DRAM_CLK,	37	37	.DRAM_CLK,
.DRAM_CS_N,	38	38	.DRAM_CS_N,
.DRAM_DQ,	39	39	.DRAM_DQ,
.DRAM_LDQM,	40	40	.DRAM_LDQM,
.DRAM_RAS_N,	41	41	.DRAM_RAS_N,
.DRAM_UDQM,	42	42	.DRAM_UDQM,
.DRAM_WE_N,	43	43	.DRAM_WE_N,
	44	44
.SW	45	45	.SW
);	46	46	);
	47	47
sdr SDR (	48	48	sdr SDR (
.Dq (DRAM_DQ),	49	49	.Dq (DRAM_DQ),
.Addr (DRAM_ADDR),	50	50	.Addr (DRAM_ADDR),
.Ba (DRAM_BA),	51	51	.Ba (DRAM_BA),
.Clk (DRAM_CLK),	52	52	.Clk (DRAM_CLK),
.Cke (DRAM_CKE),	53	53	.Cke (DRAM_CKE),
.Cs_n (DRAM_CS_N),	54	54	.Cs_n (DRAM_CS_N),
.Ras_n (DRAM_RAS_N),	55	55	.Ras_n (DRAM_RAS_N),
.Cas_n (DRAM_CAS_N),	56	56	.Cas_n (DRAM_CAS_N),
.We_n (DRAM_WE_N),	57	57	.We_n (DRAM_WE_N),
.Dqm ({DRAM_UDQM, DRAM_LDQM})	58	58	.Dqm ({DRAM_UDQM, DRAM_LDQM})
);	59	59	);
	60	60
// Generate reference clock	61	61	// Generate reference clock
always	62	62	always
begin	63	63	begin
#10 CLOCK_50 = ~CLOCK_50;	64	64	#10 CLOCK_50 = ~CLOCK_50;
end	65	65	end
	66	66
initial	67	67	initial
begin	68	68	begin
CLOCK_50 = 1'b0;	69	69	CLOCK_50 = 1'b0;
SW[0] = 1'b0; // Hard reset	70	70	SW[0] = 1'b0; // Hard reset
SW[1] = 1'b0; // Soft reset	71	71	SW[1] = 1'b0; // Soft reset
	72	72
repeat (10) @(posedge CLOCK_50); // Wait for 10 cycles	73	73	repeat (10) @(posedge CLOCK_50); // Wait for 10 cycles
SW[0] = 1'b1; // Release hard reset	74	74	SW[0] = 1'b1; // Release hard reset
	75	75
/*	76	76	/*
* Memory controller is set to wait 1us after a hard reset for the	77	77	* Memory controller is set to wait 1us after a hard reset for the
* hardware memory to stabilize. In real world this should be 100us.	78	78	* hardware memory to stabilize. In real world this should be 100us.
* Wait 2us before releasing the soft reset.	79	79	* Wait 2us before releasing the soft reset.
*/	80	80	*/
#2000 @(posedge DUT.clk);	81	81	#2000 @(posedge DUT.clk);
// Hack binary code into sdram's bank0. Please change the path	82	82	// Hack binary code into sdram's bank0. Please change the path
$readmemh("C:/path_to_project/hexfiles/nqueens.16bit.bank0.hex", SDR.Bank0);	83	83	$readmemh("../../../hexfiles/nqueens.16bit.bank0.hex", SDR.Bank0);
$readmemh("C:/path_to_project/hexfiles/nqueens.16bit.bank1.hex", SDR.Bank1);	84	84	$readmemh("../../../hexfiles/nqueens.16bit.bank1.hex", SDR.Bank1);
// Release soft reset	85	85	// Release soft reset
SW[1] = 1'b1;	86	86	SW[1] = 1'b1;
	87	87
/*	88	88	/*

/*	1	1	/*
* branch_controller.sv	2	2	* branch_controller.sv
* Author: Zinsser Zhang	3	3	* Author: Zinsser Zhang
* Last Revision: 04/08/2018	4	4	* Last Revision: 04/08/2018
*	5	5	*
* These are glue circuits in each stage. They select data between different	6	6	* These are glue circuits in each stage. They select data between different
* sources for particular signals (e.g. alu's op2). They also re-combine the	7	7	* sources for particular signals (e.g. alu's op2). They also re-combine the
* signals to different interfaces that are passed to the next stage or hazard	8	8	* signals to different interfaces that are passed to the next stage or hazard
* controller.	9	9	* controller.
*/	10	10	*/
`include "mips_core.svh"	11	11	`include "mips_core.svh"
	12	12
module decode_stage_glue (	13	13	module decode_stage_glue (
decoder_output_ifc.in i_decoded,	14	14	decoder_output_ifc.in i_decoded,
reg_file_output_ifc.in i_reg_data,	15	15	reg_file_output_ifc.in i_reg_data,
	16	16
branch_decoded_ifc.decode branch_decoded, // Contains both i/o	17	17	branch_decoded_ifc.decode branch_decoded, // Contains both i/o
	18	18
alu_input_ifc.out o_alu_input,	19	19	alu_input_ifc.out o_alu_input,
alu_pass_through_ifc.out o_alu_pass_through	20	20	alu_pass_through_ifc.out o_alu_pass_through
);	21	21	);
	22	22
always_comb	23	23	always_comb
begin	24	24	begin
o_alu_input.valid = i_decoded.valid;	25	25	o_alu_input.valid = i_decoded.valid;
o_alu_input.alu_ctl = i_decoded.alu_ctl;	26	26	o_alu_input.alu_ctl = i_decoded.alu_ctl;
o_alu_input.op1 = i_reg_data.rs_data;	27	27	o_alu_input.op1 = i_reg_data.rs_data;
o_alu_input.op2 = i_decoded.uses_immediate	28	28	o_alu_input.op2 = i_decoded.uses_immediate
? i_decoded.immediate	29	29	? i_decoded.immediate
: i_reg_data.rt_data;	30	30	: i_reg_data.rt_data;
	31	31
branch_decoded.valid = i_decoded.is_branch;	32	32	branch_decoded.valid = i_decoded.is_branch_jump;
branch_decoded.is_jump = i_decoded.is_jump;	33	33	branch_decoded.is_jump = i_decoded.is_jump;
branch_decoded.target = i_decoded.is_jump_reg	34	34	branch_decoded.target = i_decoded.is_jump_reg
? i_reg_data.rs_data[`ADDR_WIDTH - 1 : 0]	35	35	? i_reg_data.rs_data[`ADDR_WIDTH - 1 : 0]
: i_decoded.branch_target;	36	36	: i_decoded.branch_target;
	37	37
	38	38
o_alu_pass_through.is_branch = i_decoded.is_branch & ~i_decoded.is_jump;	39	39	o_alu_pass_through.is_branch = i_decoded.is_branch_jump & ~i_decoded.is_jump;
o_alu_pass_through.prediction = branch_decoded.prediction;	40	40	o_alu_pass_through.prediction = branch_decoded.prediction;
o_alu_pass_through.recovery_target = branch_decoded.recovery_target;	41	41	o_alu_pass_through.recovery_target = branch_decoded.recovery_target;
	42	42
o_alu_pass_through.is_mem_access = i_decoded.is_mem_access;	43	43	o_alu_pass_through.is_mem_access = i_decoded.is_mem_access;
o_alu_pass_through.mem_action = i_decoded.mem_action;	44	44	o_alu_pass_through.mem_action = i_decoded.mem_action;
	45	45
o_alu_pass_through.sw_data = i_reg_data.rt_data;	46	46	o_alu_pass_through.sw_data = i_reg_data.rt_data;
	47	47
o_alu_pass_through.uses_rw = i_decoded.uses_rw;	48	48	o_alu_pass_through.uses_rw = i_decoded.uses_rw;
o_alu_pass_through.rw_addr = i_decoded.rw_addr;	49	49	o_alu_pass_through.rw_addr = i_decoded.rw_addr;
end	50	50	end
endmodule	51	51	endmodule
	52	52
module ex_stage_glue (	53	53	module ex_stage_glue (
alu_output_ifc.in i_alu_output,	54	54	alu_output_ifc.in i_alu_output,
alu_pass_through_ifc.in i_alu_pass_through,	55	55	alu_pass_through_ifc.in i_alu_pass_through,
	56	56
branch_result_ifc.out o_branch_result,	57	57	branch_result_ifc.out o_branch_result,
d_cache_input_ifc.out o_d_cache_input,	58	58	d_cache_input_ifc.out o_d_cache_input,
d_cache_pass_through_ifc.out o_d_cache_pass_through	59	59	d_cache_pass_through_ifc.out o_d_cache_pass_through
);	60	60	);
	61	61
always_comb	62	62	always_comb
begin	63	63	begin
o_branch_result.valid = i_alu_output.valid	64	64	o_branch_result.valid = i_alu_output.valid
& i_alu_pass_through.is_branch;	65	65	& i_alu_pass_through.is_branch;
o_branch_result.prediction = i_alu_pass_through.prediction;	66	66	o_branch_result.prediction = i_alu_pass_through.prediction;
o_branch_result.outcome = i_alu_output.branch_outcome;	67	67	o_branch_result.outcome = i_alu_output.branch_outcome;
o_branch_result.recovery_target = i_alu_pass_through.recovery_target;	68	68	o_branch_result.recovery_target = i_alu_pass_through.recovery_target;
	69	69
o_d_cache_input.valid = i_alu_pass_through.is_mem_access;	70	70	o_d_cache_input.valid = i_alu_pass_through.is_mem_access;
o_d_cache_input.mem_action = i_alu_pass_through.mem_action;	71	71	o_d_cache_input.mem_action = i_alu_pass_through.mem_action;
o_d_cache_input.addr = i_alu_output.result[`ADDR_WIDTH - 1 : 0];	72	72	o_d_cache_input.addr = i_alu_output.result[`ADDR_WIDTH - 1 : 0];
o_d_cache_input.addr_next = i_alu_output.result[`ADDR_WIDTH - 1 : 0];	73	73	o_d_cache_input.addr_next = i_alu_output.result[`ADDR_WIDTH - 1 : 0];
o_d_cache_input.data = i_alu_pass_through.sw_data;	74	74	o_d_cache_input.data = i_alu_pass_through.sw_data;
	75	75
o_d_cache_pass_through.is_mem_access = i_alu_pass_through.is_mem_access;	76	76	o_d_cache_pass_through.is_mem_access = i_alu_pass_through.is_mem_access;
o_d_cache_pass_through.alu_result = i_alu_output.result;	77	77	o_d_cache_pass_through.alu_result = i_alu_output.result;
o_d_cache_pass_through.uses_rw = i_alu_pass_through.uses_rw;	78	78	o_d_cache_pass_through.uses_rw = i_alu_pass_through.uses_rw;
o_d_cache_pass_through.rw_addr = i_alu_pass_through.rw_addr;	79	79	o_d_cache_pass_through.rw_addr = i_alu_pass_through.rw_addr;
end	80	80	end
endmodule	81	81	endmodule
	82	82
module mem_stage_glue (	83	83	module mem_stage_glue (
cache_output_ifc.in i_d_cache_output,	84	84	cache_output_ifc.in i_d_cache_output,
d_cache_pass_through_ifc.in i_d_cache_pass_through,	85	85	d_cache_pass_through_ifc.in i_d_cache_pass_through,
	86	86