Venkataram Edavamadathil Sivaram / supermips

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Commit 0da65f785c675395c17c662413448f89f4147886

Authored by zinsser
1 parent 7373ebccf9
Exists in master and in 5 other branches baseline_v2.3, baseline_v3.0, baseline_v3.2, baseline_v3.3, origin/baseline_v2.3

Add fast simulation files.

Showing 9 changed files with 480 additions and 22 deletions Side-by-side Diff

README.md View file @ 0da65f7
1   -#CSE 148 Baseline version 2.1
2   -##Release v2.1 04/10/2018 Zinsser Zhang
  1 +# CSE 148 Baseline version 2.2
  2 +
  3 +## Release v2.2 04/12/2018 Zinsser Zhang
3 4  
4 5 Please refer to the wiki page **Walkthrough** for instructions to play around the design really quick.
5 6 Detailed documentations can be found in the wiki of this repository.
mips_cpu/fast_sdram.sv View file @ 0da65f7
  1 +/*
  2 + * fast_sdram.sv
  3 + * Author: Zinsser Zhang
  4 + * Last Revision: 04/12/2018
  5 + *
  6 + * This is a fast sdram simulation model. It is fast in terms of simulation
  7 + * speed. This module should only be used to verify the functionality of your
  8 + * design. And it is not guaranteed that your design can pass the full
  9 + * simulation if it passes the fast simulation. You still need to run the full
  10 + * simulation to make sure everything works. Performance measurement should also
  11 + * be done with the full simulation.
  12 + *
  13 + * See wiki page "Speed up Simulation" for details.
  14 + */
  15 +`timescale 1ns / 1ps
  16 +`include "mips_cpu.svh"
  17 +
  18 +module fast_sdram #(parameter DELAY = 20)(
  19 + // General signals
  20 + input clk, // Clock
  21 + input rst_n, // Asynchronous reset active low
  22 +
  23 + // Memory interfaces
  24 + mem_read_ifc.response i_cache_read,
  25 + mem_write_ifc.response d_cache_write,
  26 + mem_read_ifc.response d_cache_read
  27 +);
  28 +
  29 + logic [`DATA_WIDTH - 1 : 0] mem [1 << (`ADDR_WIDTH - 2)];
  30 +
  31 + logic rst;
  32 + assign rst = ~rst_n;
  33 +
  34 + logic odd_cycle;
  35 +
  36 + enum {
  37 + STATE_IDLE,
  38 + STATE_DELAY,
  39 + STATE_SERVE_IREAD,
  40 + STATE_SERVE_DREAD,
  41 + STATE_SERVE_DWRITE
  42 + } state, next_state;
  43 +
  44 + integer delay_counter;
  45 + logic ir_pending, dr_pending, dw_pending;
  46 +
  47 + assign i_cache_read.control_done = ~ir_pending;
  48 + assign d_cache_read.control_done = ~dr_pending;
  49 + assign d_cache_write.control_done = ~dw_pending;
  50 +
  51 + logic [`ADDR_WIDTH - 1 : 0] pointer, pending_length;
  52 + logic [`ADDR_WIDTH - 1 : 0] ir_base, ir_length;
  53 + logic [`ADDR_WIDTH - 1 : 0] dr_base, dr_length;
  54 + logic [`ADDR_WIDTH - 1 : 0] dw_base, dw_length;
  55 +
  56 +
  57 + logic [`DATA_WIDTH - 1 : 0] iread_data, dread_data, dwrite_data;
  58 + logic iread_empty, iread_full, iread_we;
  59 + logic dread_empty, dread_full, dread_we;
  60 + logic dwrite_empty, dwrite_full, dwrite_re;
  61 +
  62 + assign iread_data = mem[pointer[2 +: `ADDR_WIDTH - 2]];
  63 + assign dread_data = mem[pointer[2 +: `ADDR_WIDTH - 2]];
  64 +
  65 + assign i_cache_read.user_available = ~iread_empty;
  66 + scfifo iread_fifo (
  67 + .aclr (rst),
  68 + .clock (clk),
  69 + .empty (iread_empty),
  70 + .full (iread_full),
  71 + .data (iread_data),
  72 + .q (i_cache_read.user_data),
  73 + .rdreq (i_cache_read.user_re),
  74 + .wrreq (iread_we)
  75 + );
  76 + defparam iread_fifo.add_ram_output_register = "OFF",
  77 + iread_fifo.intended_device_family = "Cyclone V",
  78 + iread_fifo.lpm_numwords = 32,
  79 + iread_fifo.lpm_showahead = "ON",
  80 + iread_fifo.lpm_type = "scfifo",
  81 + iread_fifo.lpm_width = `DATA_WIDTH,
  82 + iread_fifo.lpm_widthu = 5,
  83 + iread_fifo.overflow_checking = "OFF",
  84 + iread_fifo.underflow_checking = "OFF",
  85 + iread_fifo.use_eab = "ON";
  86 +
  87 + assign d_cache_read.user_available = ~dread_empty;
  88 + scfifo dread_fifo (
  89 + .aclr (rst),
  90 + .clock (clk),
  91 + .empty (dread_empty),
  92 + .full (dread_full),
  93 + .data (dread_data),
  94 + .q (d_cache_read.user_data),
  95 + .rdreq (d_cache_read.user_re),
  96 + .wrreq (dread_we)
  97 + );
  98 + defparam dread_fifo.add_ram_output_register = "OFF",
  99 + dread_fifo.intended_device_family = "Cyclone V",
  100 + dread_fifo.lpm_numwords = 32,
  101 + dread_fifo.lpm_showahead = "ON",
  102 + dread_fifo.lpm_type = "scfifo",
  103 + dread_fifo.lpm_width = `DATA_WIDTH,
  104 + dread_fifo.lpm_widthu = 5,
  105 + dread_fifo.overflow_checking = "OFF",
  106 + dread_fifo.underflow_checking = "OFF",
  107 + dread_fifo.use_eab = "ON";
  108 +
  109 + assign d_cache_write.user_full = dwrite_full;
  110 + scfifo dwrite_fifo (
  111 + .aclr (rst),
  112 + .clock (clk),
  113 + .empty (dwrite_empty),
  114 + .full (dwrite_full),
  115 + .data (d_cache_write.user_data),
  116 + .q (dwrite_data),
  117 + .rdreq (dwrite_re),
  118 + .wrreq (d_cache_write.user_we)
  119 + );
  120 + defparam dwrite_fifo.add_ram_output_register = "OFF",
  121 + dwrite_fifo.intended_device_family = "Cyclone V",
  122 + dwrite_fifo.lpm_numwords = 32,
  123 + dwrite_fifo.lpm_showahead = "ON",
  124 + dwrite_fifo.lpm_type = "scfifo",
  125 + dwrite_fifo.lpm_width = `DATA_WIDTH,
  126 + dwrite_fifo.lpm_widthu = 5,
  127 + dwrite_fifo.overflow_checking = "OFF",
  128 + dwrite_fifo.underflow_checking = "OFF",
  129 + dwrite_fifo.use_eab = "ON";
  130 +
  131 + assign iread_we = (state == STATE_SERVE_IREAD ) && (pending_length != '0) && !iread_full && odd_cycle;
  132 + assign dread_we = (state == STATE_SERVE_DREAD ) && (pending_length != '0) && !dread_full && ~odd_cycle;
  133 + assign dwrite_re = (state == STATE_SERVE_DWRITE) && (pending_length != '0) && !dwrite_empty;
  134 +
  135 + always_comb
  136 + begin
  137 + next_state <= state;
  138 +
  139 + case (state)
  140 + STATE_IDLE:
  141 + begin
  142 + if (ir_pending | dr_pending | dw_pending)
  143 + next_state <= STATE_DELAY;
  144 + end
  145 +
  146 + STATE_DELAY:
  147 + begin
  148 + if (delay_counter == 0)
  149 + begin
  150 + if (ir_pending) next_state <= STATE_SERVE_IREAD;
  151 + else if (dr_pending) next_state <= STATE_SERVE_DREAD;
  152 + else if (dw_pending) next_state <= STATE_SERVE_DWRITE;
  153 + end
  154 + end
  155 +
  156 + default: if (pending_length == '0) next_state <= STATE_IDLE;
  157 + endcase
  158 + end
  159 +
  160 +
  161 + always_ff @(posedge clk or negedge rst_n)
  162 + begin
  163 + if(~rst_n)
  164 + begin
  165 + state <= STATE_IDLE;
  166 + delay_counter <= 0;
  167 + pending_length <= '0;
  168 + ir_pending <= 1'b0;
  169 + dr_pending <= 1'b0;
  170 + dw_pending <= 1'b0;
  171 + odd_cycle <= 1'b0;
  172 + end
  173 + else
  174 + begin
  175 + odd_cycle <= ~odd_cycle;
  176 + state <= next_state;
  177 + if (i_cache_read.control_go)
  178 + begin
  179 + ir_pending <= 1'b1;
  180 + ir_base <= i_cache_read.control_base;
  181 + ir_length <= i_cache_read.control_length;
  182 + end
  183 +
  184 + if (d_cache_read.control_go)
  185 + begin
  186 + dr_pending <= 1'b1;
  187 + dr_base <= d_cache_read.control_base;
  188 + dr_length <= d_cache_read.control_length;
  189 + end
  190 +
  191 + if (d_cache_write.control_go)
  192 + begin
  193 + dw_pending <= 1'b1;
  194 + dw_base <= d_cache_write.control_base;
  195 + dw_length <= d_cache_write.control_length;
  196 + end
  197 +
  198 + case (state)
  199 + STATE_IDLE:
  200 + begin
  201 + if (next_state == STATE_DELAY)
  202 + delay_counter <= DELAY;
  203 + end
  204 +
  205 + STATE_DELAY:
  206 + begin
  207 + if (delay_counter > 0)
  208 + delay_counter <= delay_counter - 1;
  209 + else
  210 + begin
  211 + if (next_state == STATE_SERVE_IREAD)
  212 + begin
  213 + pointer <= ir_base;
  214 + pending_length <= ir_length;
  215 + end
  216 + else if (next_state == STATE_SERVE_DREAD)
  217 + begin
  218 + pointer <= dr_base;
  219 + pending_length <= dr_length;
  220 + end
  221 + else if (next_state == STATE_SERVE_DWRITE)
  222 + begin
  223 + pointer <= dw_base;
  224 + pending_length <= dw_length;
  225 + end
  226 + end
  227 + end
  228 +
  229 + STATE_SERVE_IREAD:
  230 + begin
  231 + if (next_state == STATE_IDLE) ir_pending <= 1'b0;
  232 + else if (iread_we)
  233 + begin
  234 + pointer <= pointer + `ADDR_WIDTH'd4;
  235 + pending_length <= pending_length - `ADDR_WIDTH'd4;
  236 + end
  237 + end
  238 +
  239 + STATE_SERVE_DREAD:
  240 + begin
  241 + if (next_state == STATE_IDLE) dr_pending <= 1'b0;
  242 + else if (dread_we)
  243 + begin
  244 + pointer <= pointer + `ADDR_WIDTH'd4;
  245 + pending_length <= pending_length - `ADDR_WIDTH'd4;
  246 + end
  247 + end
  248 +
  249 + STATE_SERVE_DWRITE:
  250 + begin
  251 + if (next_state == STATE_IDLE) dw_pending <= 1'b0;
  252 + else if (dwrite_re)
  253 + begin
  254 + pointer <= pointer + `ADDR_WIDTH'd4;
  255 + pending_length <= pending_length - `ADDR_WIDTH'd4;
  256 + mem[pointer[2 +: `ADDR_WIDTH - 2]] <= dwrite_data;
  257 + end
  258 + end
  259 + endcase
  260 + end
  261 + end
  262 +endmodule
mips_cpu/fast_testbench.do View file @ 0da65f7
  1 +# fast_testbench.do
  2 +# Author: Zinsser Zhang
  3 +# Last Revision: 04/12/2018
  4 +
  5 +# Compile the testbench
  6 +vlog -reportprogress 300 -work work ../../fast_testbench.sv
  7 +
  8 +# Compile the simulation model of sdram
  9 +vlog -reportprogress 300 -work work ../../fast_sdram.sv
  10 +
  11 +# Start the simulation of testbench with all the linking flags to other libs
  12 +vsim -t ns -L altera_mf_ver fast_testbench
mips_cpu/fast_testbench.sv View file @ 0da65f7
  1 +/*
  2 + * fast_testbench.sv
  3 + * Author: Zinsser Zhang
  4 + * Last Revision: 04/12/2018
  5 + *
  6 + * This is a fast simulation testbench. It is fast in terms of simulation
  7 + * speed. This module should only be used to verify the functionality of your
  8 + * design. And it is not guaranteed that your design can pass the full
  9 + * simulation if it passes the fast simulation. You still need to run the full
  10 + * simulation to make sure everything works. Performance measurement should also
  11 + * be done with the full simulation.
  12 + *
  13 + * See wiki page "Speed up Simulation" for details.
  14 + */
  15 +`timescale 1 ns / 1 ps
  16 +`include "mips_cpu.svh"
  17 +
  18 +module fast_testbench ();
  19 +
  20 + logic clk, rst_n;
  21 + mem_read_ifc i_cache_read();
  22 + mem_write_ifc d_cache_write();
  23 + mem_read_ifc d_cache_read();
  24 +
  25 + pass_done_ifc pass_done();
  26 +
  27 +
  28 + mips_core MIPS_CORE (
  29 + .clk, .rst_n,
  30 +
  31 + .i_cache_read,
  32 + .d_cache_write,
  33 + .d_cache_read,
  34 +
  35 + .pass_done
  36 + );
  37 +
  38 + fast_sdram FAST_SDRAM (
  39 + .clk, .rst_n,
  40 +
  41 + .i_cache_read,
  42 + .d_cache_write,
  43 + .d_cache_read
  44 + );
  45 + defparam FAST_SDRAM.DELAY = 20;
  46 +
  47 + // Generate reference clock
  48 + always
  49 + begin
  50 + #5 clk = ~clk;
  51 + end
  52 +
  53 + initial
  54 + begin
  55 + clk = 1'b0;
  56 + rst_n = 1'b0;
  57 +
  58 + repeat (10) @(posedge clk); // Wait for 10 cycles
  59 + rst_n = 1'b1; // Release reset
  60 +
  61 + // Load binary code
  62 + $readmemh("../../../hexfiles/nqueens.hex", FAST_SDRAM.mem);
  63 +
  64 + /*
  65 + * Stop the simulation so that you can step through from the beginning.
  66 + * Click run to step and run all again to continue the simulation.
  67 + * Comment out the following line if you don't want to break here.
  68 + */
  69 + $stop;
  70 +
  71 + // Wait for the mips_core to report a fail or done MTC0 instruction
  72 + wait(pass_done.code == MTC0_FAIL || pass_done.code == MTC0_DONE);
  73 + $stop;
  74 + end
  75 +endmodule
mips_cpu/fast_wave.do View file @ 0da65f7
  1 +onerror {resume}
  2 +quietly WaveActivateNextPane {} 0
  3 +add wave -noupdate -divider {IF Stage}
  4 +add wave -noupdate /fast_testbench/MIPS_CORE/clk
  5 +add wave -noupdate /fast_testbench/MIPS_CORE/rst_n
  6 +add wave -noupdate /fast_testbench/MIPS_CORE/i2i_hc/stall
  7 +add wave -noupdate -color {Slate Blue} -radix hexadecimal /fast_testbench/MIPS_CORE/if_pc_current/pc
  8 +add wave -noupdate -color {Slate Blue} -radix hexadecimal /fast_testbench/MIPS_CORE/if_pc_next/pc
  9 +add wave -noupdate /fast_testbench/MIPS_CORE/if_i_cache_output/valid
  10 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/if_i_cache_output/data
  11 +add wave -noupdate -divider {IF to DEC}
  12 +add wave -noupdate /fast_testbench/MIPS_CORE/i2d_hc/flush
  13 +add wave -noupdate /fast_testbench/MIPS_CORE/i2d_hc/stall
  14 +add wave -noupdate -divider {DEC Stage}
  15 +add wave -noupdate /fast_testbench/MIPS_CORE/clk
  16 +add wave -noupdate -color {Slate Blue} -radix hexadecimal /fast_testbench/MIPS_CORE/i2d_pc/pc
  17 +add wave -noupdate /fast_testbench/MIPS_CORE/i2d_inst/valid
  18 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/i2d_inst/data
  19 +add wave -noupdate -divider <NULL>
  20 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/valid
  21 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/alu_ctl
  22 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/is_branch_jump
  23 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/is_jump
  24 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/is_jump_reg
  25 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/dec_decoder_output/branch_target
  26 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/is_mem_access
  27 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/mem_action
  28 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/uses_rs
  29 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/rs_addr
  30 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/uses_rt
  31 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/rt_addr
  32 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/uses_immediate
  33 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/dec_decoder_output/immediate
  34 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/uses_rw
  35 +add wave -noupdate /fast_testbench/MIPS_CORE/dec_decoder_output/rw_addr
  36 +add wave -noupdate -divider <NULL>
  37 +add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/valid
  38 +add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/is_jump
  39 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/target
  40 +add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/prediction
  41 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/recovery_target
  42 +add wave -noupdate -divider <NULL>
  43 +add wave -noupdate -color Cyan -radix hexadecimal -childformat {{{/fast_testbench/MIPS_CORE/REG_FILE/regs[0]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[1]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[2]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[3]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[4]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[5]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[6]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[7]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[8]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[9]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[10]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[11]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[12]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[13]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[14]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[15]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[16]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[17]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[18]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[19]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[20]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[21]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[22]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[23]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[24]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[25]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[26]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[27]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[28]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[29]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[30]} -radix hexadecimal} {{/fast_testbench/MIPS_CORE/REG_FILE/regs[31]} -radix hexadecimal}} -expand -subitemconfig {{/fast_testbench/MIPS_CORE/REG_FILE/regs[0]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[1]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[2]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[3]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[4]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[5]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[6]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[7]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[8]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[9]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[10]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[11]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[12]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[13]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[14]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[15]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[16]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[17]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[18]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[19]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[20]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[21]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[22]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[23]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[24]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[25]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[26]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[27]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[28]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[29]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[30]} {-color Cyan -radix hexadecimal} {/fast_testbench/MIPS_CORE/REG_FILE/regs[31]} {-color Cyan -radix hexadecimal}} /fast_testbench/MIPS_CORE/REG_FILE/regs
  44 +add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/o_alu_input/valid
  45 +add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/o_alu_input/alu_ctl
  46 +add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/o_alu_input/op1
  47 +add wave -noupdate /fast_testbench/MIPS_CORE/DEC_STAGE_GLUE/o_alu_input/op2
  48 +add wave -noupdate -divider {DEC to EX}
  49 +add wave -noupdate /fast_testbench/MIPS_CORE/d2e_hc/flush
  50 +add wave -noupdate /fast_testbench/MIPS_CORE/d2e_hc/stall
  51 +add wave -noupdate -divider {EX Stage}
  52 +add wave -noupdate /fast_testbench/MIPS_CORE/clk
  53 +add wave -noupdate -color {Slate Blue} -radix hexadecimal /fast_testbench/MIPS_CORE/d2e_pc/pc
  54 +add wave -noupdate /fast_testbench/MIPS_CORE/ex_alu_output/valid
  55 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/ex_alu_output/result
  56 +add wave -noupdate /fast_testbench/MIPS_CORE/ex_alu_output/branch_outcome
  57 +add wave -noupdate -divider <NULL>
  58 +add wave -noupdate /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/valid
  59 +add wave -noupdate /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/prediction
  60 +add wave -noupdate /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/outcome
  61 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/recovery_target
  62 +add wave -noupdate /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/valid
  63 +add wave -noupdate /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/mem_action
  64 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/addr
  65 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/addr_next
  66 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/data
  67 +add wave -noupdate -divider {EX to MEM}
  68 +add wave -noupdate /fast_testbench/MIPS_CORE/e2m_hc/flush
  69 +add wave -noupdate /fast_testbench/MIPS_CORE/e2m_hc/stall
  70 +add wave -noupdate -divider {MEM Stage}
  71 +add wave -noupdate /fast_testbench/MIPS_CORE/clk
  72 +add wave -noupdate -color {Slate Blue} -radix hexadecimal /fast_testbench/MIPS_CORE/e2m_pc/pc
  73 +add wave -noupdate /fast_testbench/MIPS_CORE/mem_d_cache_output/valid
  74 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/mem_d_cache_output/data
  75 +add wave -noupdate -divider {MEM to WB}
  76 +add wave -noupdate /fast_testbench/MIPS_CORE/m2w_hc/flush
  77 +add wave -noupdate /fast_testbench/MIPS_CORE/m2w_hc/stall
  78 +add wave -noupdate -divider {WB Stage}
  79 +add wave -noupdate /fast_testbench/MIPS_CORE/clk
  80 +add wave -noupdate /fast_testbench/MIPS_CORE/m2w_write_back/uses_rw
  81 +add wave -noupdate /fast_testbench/MIPS_CORE/m2w_write_back/rw_addr
  82 +add wave -noupdate -radix hexadecimal /fast_testbench/MIPS_CORE/m2w_write_back/rw_data
  83 +add wave -noupdate -divider Hazards
  84 +add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/lw_hazard
  85 +add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/ic_miss
  86 +add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/ds_miss
  87 +add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/dec_overload
  88 +add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/ex_overload
  89 +add wave -noupdate /fast_testbench/MIPS_CORE/HAZARD_CONTROLLER/dc_miss
  90 +TreeUpdate [SetDefaultTree]
  91 +WaveRestoreCursors {{Cursor 1} {36408825 ps} 0}
  92 +quietly wave cursor active 1
  93 +configure wave -namecolwidth 386
  94 +configure wave -valuecolwidth 100
  95 +configure wave -justifyvalue left
  96 +configure wave -signalnamewidth 0
  97 +configure wave -snapdistance 10
  98 +configure wave -datasetprefix 0
  99 +configure wave -rowmargin 4
  100 +configure wave -childrowmargin 2
  101 +configure wave -gridoffset 0
  102 +configure wave -gridperiod 1
  103 +configure wave -griddelta 40
  104 +configure wave -timeline 0
  105 +configure wave -timelineunits ns
  106 +update
  107 +WaveRestoreZoom {3531792904 ps} {3531863532 ps}
mips_cpu/mips_core/decoder.sv View file @ 0da65f7
... ... @@ -14,7 +14,7 @@
14 14 interface decoder_output_ifc ();
15 15 logic valid;
16 16 mips_core_pkg::AluCtl alu_ctl;
17   - logic is_branch;
  17 + logic is_branch_jump;
18 18 logic is_jump;
19 19 logic is_jump_reg;
20 20 logic [`ADDR_WIDTH - 1 : 0] branch_target;
21 21  
... ... @@ -34,10 +34,10 @@
34 34 logic uses_rw;
35 35 mips_core_pkg::MipsReg rw_addr;
36 36  
37   - modport in (input valid, alu_ctl, is_branch, is_jump, is_jump_reg,
  37 + modport in (input valid, alu_ctl, is_branch_jump, is_jump, is_jump_reg,
38 38 branch_target, is_mem_access, mem_action, uses_rs, rs_addr, uses_rt,
39 39 rt_addr, uses_immediate, immediate, uses_rw, rw_addr);
40   - modport out (output valid, alu_ctl, is_branch, is_jump, is_jump_reg,
  40 + modport out (output valid, alu_ctl, is_branch_jump, is_jump, is_jump_reg,
41 41 branch_target, is_mem_access, mem_action, uses_rs, rs_addr, uses_rt,
42 42 rt_addr, uses_immediate, immediate, uses_rw, rw_addr);
43 43 endinterface
... ... @@ -150,7 +150,7 @@
150 150 // Set defaults to nop
151 151 out.valid <= i_inst.valid;
152 152 out.alu_ctl <= ALUCTL_NOP;
153   - out.is_branch <= 1'b0;
  153 + out.is_branch_jump <= 1'b0;
154 154 out.is_jump <= 1'b0;
155 155 out.is_jump_reg <= 1'b0;
156 156 out.branch_target <= '0;
... ... @@ -275,7 +275,7 @@
275 275 begin
276 276 out.alu_ctl <= ALUCTL_NOP; // jr does not use alu
277 277 uses_rs();
278   - out.is_branch <= 1'b1;
  278 + out.is_branch_jump <= 1'b1;
279 279 out.is_jump <= 1'b1;
280 280 out.is_jump_reg <= 1'b1;
281 281 end
... ... @@ -286,7 +286,7 @@
286 286 uses_rs();
287 287 uses_rw_raw(ra); // jalr always write to ra (31)
288 288 uses_immediate_raw(32'(unsigned'(i_pc.pc)) + 8);
289   - out.is_branch <= 1'b1;
  289 + out.is_branch_jump <= 1'b1;
290 290 out.is_jump <= 1'b1;
291 291 out.is_jump_reg <= 1'b1;
292 292 end
... ... @@ -377,7 +377,7 @@
377 377 out.alu_ctl <= ALUCTL_BEQ;
378 378 uses_rs();
379 379 uses_rt();
380   - out.is_branch <= 1'b1;
  380 + out.is_branch_jump <= 1'b1;
381 381 out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);
382 382 end
383 383  
... ... @@ -386,7 +386,7 @@
386 386 out.alu_ctl <= ALUCTL_BNE;
387 387 uses_rs();
388 388 uses_rt();
389   - out.is_branch <= 1'b1;
  389 + out.is_branch_jump <= 1'b1;
390 390 out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);
391 391 end
392 392  
... ... @@ -395,7 +395,7 @@
395 395 out.alu_ctl <= ALUCTL_BLEZ;
396 396 uses_rs();
397 397 uses_rt();
398   - out.is_branch <= 1'b1;
  398 + out.is_branch_jump <= 1'b1;
399 399 out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);
400 400 end
401 401  
... ... @@ -407,7 +407,7 @@
407 407 out.alu_ctl <= ALUCTL_BLTZ;
408 408 uses_rs();
409 409 uses_rt();
410   - out.is_branch <= 1'b1;
  410 + out.is_branch_jump <= 1'b1;
411 411 out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);
412 412 end
413 413  
414 414  
... ... @@ -416,14 +416,14 @@
416 416 out.alu_ctl <= ALUCTL_BGTZ;
417 417 uses_rs();
418 418 uses_rt();
419   - out.is_branch <= 1'b1;
  419 + out.is_branch_jump <= 1'b1;
420 420 out.branch_target <= i_pc.pc + `ADDR_WIDTH'd4 + `ADDR_WIDTH'(signed'(i_inst.data[15:0]) << 2);
421 421 end
422 422  
423 423 6'h02: // j
424 424 begin
425 425 out.alu_ctl <= ALUCTL_NOP; // jr does not use alu
426   - out.is_branch <= 1'b1;
  426 + out.is_branch_jump <= 1'b1;
427 427 out.is_jump <= 1'b1;
428 428 out.branch_target <= {i_inst.data[`ADDR_WIDTH - 3: 0], 2'b00};
429 429 end
... ... @@ -433,7 +433,7 @@
433 433 out.alu_ctl <= ALUCTL_OR;
434 434 uses_rw_raw(ra); // jal always write to ra (31)
435 435 uses_immediate_raw(32'(unsigned'(i_pc.pc)) + 8);
436   - out.is_branch <= 1'b1;
  436 + out.is_branch_jump <= 1'b1;
437 437 out.is_jump <= 1'b1;
438 438 out.branch_target <= {i_inst.data[`ADDR_WIDTH - 3: 0], 2'b00};
439 439 end
mips_cpu/mips_core/glue_circuits.sv View file @ 0da65f7
... ... @@ -29,14 +29,14 @@
29 29 ? i_decoded.immediate
30 30 : i_reg_data.rt_data;
31 31  
32   - branch_decoded.valid = i_decoded.is_branch;
  32 + branch_decoded.valid = i_decoded.is_branch_jump;
33 33 branch_decoded.is_jump = i_decoded.is_jump;
34 34 branch_decoded.target = i_decoded.is_jump_reg
35 35 ? i_reg_data.rs_data[`ADDR_WIDTH - 1 : 0]
36 36 : i_decoded.branch_target;
37 37  
38 38  
39   - o_alu_pass_through.is_branch = i_decoded.is_branch & ~i_decoded.is_jump;
  39 + o_alu_pass_through.is_branch = i_decoded.is_branch_jump & ~i_decoded.is_jump;
40 40 o_alu_pass_through.prediction = branch_decoded.prediction;
41 41 o_alu_pass_through.recovery_target = branch_decoded.recovery_target;
42 42  
mips_cpu/testbench.sv View file @ 0da65f7
... ... @@ -80,8 +80,8 @@
80 80 */
81 81 #2000 @(posedge DUT.clk);
82 82 // Hack binary code into sdram's bank0. Please change the path
83   - $readmemh("C:/path_to_project/hexfiles/nqueens.16bit.bank0.hex", SDR.Bank0);
84   - $readmemh("C:/path_to_project/hexfiles/nqueens.16bit.bank1.hex", SDR.Bank1);
  83 + $readmemh("../../../hexfiles/nqueens.16bit.bank0.hex", SDR.Bank0);
  84 + $readmemh("../../../hexfiles/nqueens.16bit.bank1.hex", SDR.Bank1);
85 85 // Release soft reset
86 86 SW[1] = 1'b1;
87 87  
mips_cpu/wave.do View file @ 0da65f7
... ... @@ -19,7 +19,7 @@
19 19 add wave -noupdate -divider <NULL>
20 20 add wave -noupdate /testbench/DUT/MIPS_CORE/dec_decoder_output/valid
21 21 add wave -noupdate /testbench/DUT/MIPS_CORE/dec_decoder_output/alu_ctl
22   -add wave -noupdate /testbench/DUT/MIPS_CORE/dec_decoder_output/is_branch
  22 +add wave -noupdate /testbench/DUT/MIPS_CORE/dec_decoder_output/is_branch_jump
23 23 add wave -noupdate /testbench/DUT/MIPS_CORE/dec_decoder_output/is_jump
24 24 add wave -noupdate /testbench/DUT/MIPS_CORE/dec_decoder_output/is_jump_reg
25 25 add wave -noupdate -radix hexadecimal /testbench/DUT/MIPS_CORE/dec_decoder_output/branch_target
... ... @@ -38,7 +38,7 @@
38 38 add wave -noupdate /testbench/DUT/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/is_jump
39 39 add wave -noupdate -radix hexadecimal /testbench/DUT/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/target
40 40 add wave -noupdate /testbench/DUT/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/prediction
41   -add wave -noupdate -radix hexadecimal /testbench/DUT/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/target_post_predict
  41 +add wave -noupdate -radix hexadecimal /testbench/DUT/MIPS_CORE/DEC_STAGE_GLUE/branch_decoded/recovery_target
42 42 add wave -noupdate -divider <NULL>
43 43 add wave -noupdate -color Cyan -radix hexadecimal -childformat {{{/testbench/DUT/MIPS_CORE/REG_FILE/regs[0]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[1]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[2]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[3]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[4]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[5]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[6]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[7]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[8]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[9]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[10]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[11]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[12]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[13]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[14]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[15]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[16]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[17]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[18]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[19]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[20]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[21]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[22]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[23]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[24]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[25]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[26]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[27]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[28]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[29]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[30]} -radix hexadecimal} {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[31]} -radix hexadecimal}} -expand -subitemconfig {{/testbench/DUT/MIPS_CORE/REG_FILE/regs[0]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[1]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[2]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[3]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[4]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[5]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[6]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[7]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[8]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[9]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[10]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[11]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[12]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[13]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[14]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[15]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[16]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[17]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[18]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[19]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[20]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[21]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[22]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[23]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[24]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[25]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[26]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[27]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[28]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[29]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[30]} {-color Cyan -radix hexadecimal} {/testbench/DUT/MIPS_CORE/REG_FILE/regs[31]} {-color Cyan -radix hexadecimal}} /testbench/DUT/MIPS_CORE/REG_FILE/regs
44 44 add wave -noupdate /testbench/DUT/MIPS_CORE/DEC_STAGE_GLUE/o_alu_input/valid
... ... @@ -58,7 +58,7 @@
58 58 add wave -noupdate /testbench/DUT/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/valid
59 59 add wave -noupdate /testbench/DUT/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/prediction
60 60 add wave -noupdate /testbench/DUT/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/outcome
61   -add wave -noupdate -radix hexadecimal /testbench/DUT/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/target
  61 +add wave -noupdate -radix hexadecimal /testbench/DUT/MIPS_CORE/EX_STAGE_GLUE/o_branch_result/recovery_target
62 62 add wave -noupdate /testbench/DUT/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/valid
63 63 add wave -noupdate /testbench/DUT/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/mem_action
64 64 add wave -noupdate -radix hexadecimal /testbench/DUT/MIPS_CORE/EX_STAGE_GLUE/o_d_cache_input/addr