Commit 6cd4595171dc687b46f8b060bad02e1609dcd41d
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update synth
Showing 1 changed file with 4 additions and 4 deletions Side-by-side Diff
mips_cpu/synth/Makefile
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6cd4595
| ... | ... | @@ -10,7 +10,7 @@ |
| 10 | 10 | all: netlist.v |
| 11 | 11 | |
| 12 | 12 | mips_core.v: ../mips_core/*.sv |
| 13 | - $(CSE148_TOOLS)/sv2v-Linux/sv2v -Imips_core ../mips_core/*.sv > $@ | |
| 13 | + $(CSE148_TOOLS)/sv2v/bin/sv2v -Imips_core ../mips_core/*.sv > $@ | |
| 14 | 14 | |
| 15 | 15 | hierarchy.json: mips_core.v |
| 16 | 16 | bash -c "source $(CSE148_TOOLS)/oss-cad-suite/environment && yosys -s hierarchy.ys -l hierarchy.log -t" |
| ... | ... | @@ -23,9 +23,9 @@ |
| 23 | 23 | build/sram_%_freepdk45_analytical_TT_1p0V_25C.lib : config.py |
| 24 | 24 | env RAM_CONFIG="$*" \ |
| 25 | 25 | FREEPDK45=$(CSE148_TOOLS)/FreePDK45 \ |
| 26 | - OPENRAM_HOME=$(CSE148_TOOLS)/OpenRAM/compiler \ | |
| 27 | - OPENRAM_TECH=$(CSE148_TOOLS)/OpenRAM/technology \ | |
| 28 | - python3 $(CSE148_TOOLS)/OpenRAM/compiler/openram.py config | |
| 26 | + OPENRAM_HOME=$(CSE148_TOOLS)/OpenRAM-1.2.45/compiler \ | |
| 27 | + OPENRAM_TECH=$(CSE148_TOOLS)/OpenRAM-1.2.45/technology \ | |
| 28 | + python3 $(CSE148_TOOLS)/OpenRAM-1.2.45/sram_compiler.py config | |
| 29 | 29 | |
| 30 | 30 | netlist.v: mips_core.v $(ram_targets) synthesis.ys |
| 31 | 31 | bash -c "source $(CSE148_TOOLS)/oss-cad-suite/environment && yosys -s synthesis.ys -l synthesis.log -t" |