Venkataram Edavamadathil Sivaram / supermips

Download as
Browse Code ยป

Commit b07f70ada3aed7476189bc54d19d422c5f52e9cd

Authored by zinsser
1 parent bec01f1540
Exists in master and in 5 other branches baseline_v2.3, baseline_v3.0, baseline_v3.2, baseline_v3.3, origin/baseline_v2.3

Fixed a Verilog non-compliant bug.

Showing 2 changed files with 22 additions and 16 deletions Side-by-side Diff

src/core_memory_arbiter.v View file @ b07f70a
... ... @@ -18,14 +18,14 @@
18 18 // General
19 19 input i_Clk,
20 20 input i_Reset_n,
21   -
  21 +
22 22 // Requests to/from IMEM - Assume we always read
23 23 input i_IMEM_Valid, // If IMEM request is valid
24 24 input [ADDRESS_WIDTH-1:0] i_IMEM_Address, // IMEM request addr.
25 25 output reg o_IMEM_Valid,
26 26 output reg o_IMEM_Last,
27 27 output reg [DATA_WIDTH-1:0] o_IMEM_Data,
28   -
  28 +
29 29 // Requests to/from DMEM
30 30 input i_DMEM_Valid,
31 31 input i_DMEM_Read_Write_n,
32 32  
33 33  
34 34  
35 35  
36 36  
37 37  
... ... @@ -35,34 +35,34 @@
35 35 output reg o_DMEM_Data_Read,
36 36 output reg o_DMEM_Last,
37 37 output reg [DATA_WIDTH-1:0] o_DMEM_Data,
38   -
  38 +
39 39 // Interface to outside of the core
40 40 output reg o_MEM_Valid,
41 41 output reg [ADDRESS_WIDTH-1:0] o_MEM_Address,
42 42 output reg o_MEM_Read_Write_n,
43   -
  43 +
44 44 // Write data interface
45 45 output reg [DATA_WIDTH-1:0] o_MEM_Data,
46 46 input i_MEM_Data_Read,
47   -
  47 +
48 48 // Read data interface
49 49 input [DATA_WIDTH-1:0] i_MEM_Data,
50 50 input i_MEM_Valid,
51   -
  51 +
52 52 input i_MEM_Last // If we're on the last piece of the transaction
53 53 );
54   -
  54 +
55 55 // Consts
56 56 localparam TRUE = 1'b1;
57 57 localparam FALSE = 1'b0;
58 58 localparam READ = 1'b1;
59   - localparam WRITE = 1'b0;
60   -
  59 + localparam WRITE = 1'b0;
  60 +
61 61 // State of the arbiter
62 62 localparam STATE_READY = 4'd0;
63 63 localparam STATE_SERVICING_IMEM = 4'd1;
64 64 localparam STATE_SERVICING_DMEM = 4'd2;
65   -
  65 +
66 66 reg [3:0] State;
67 67 reg [3:0] NextState;
68 68  
69 69  
... ... @@ -90,7 +90,10 @@
90 90 NextState <= STATE_READY;
91 91 end
92 92 endcase
  93 + end
93 94  
  95 + always @(*)
  96 + begin
94 97 o_IMEM_Valid <= FALSE;
95 98 o_IMEM_Last <= FALSE;
96 99 o_IMEM_Data <= {32{1'bx}};
... ... @@ -110,7 +113,7 @@
110 113 o_MEM_Read_Write_n <= READ;
111 114 o_IMEM_Valid <= i_MEM_Valid;
112 115 o_IMEM_Last <= i_MEM_Last;
113   - o_IMEM_Data <= i_MEM_Data;
  116 + o_IMEM_Data <= i_MEM_Data;
114 117 end
115 118 else if (State == STATE_SERVICING_DMEM || NextState == STATE_SERVICING_DMEM)
116 119 begin
117 120  
118 121  
... ... @@ -124,16 +127,16 @@
124 127 o_DMEM_Data <= i_MEM_Data;
125 128 end
126 129 end
127   -
  130 +
128 131 // State driver
129 132 always @(posedge i_Clk or negedge i_Reset_n)
130 133 begin
131 134 if( !i_Reset_n )
132   - // Defaults
133   - State <= STATE_READY;
  135 + // Defaults
  136 + State <= STATE_READY;
134 137 else
135 138 State <= NextState;
136 139 end
137   -
  140 +
138 141 endmodule
src/memory_arbiter.v View file @ b07f70a
... ... @@ -89,7 +89,10 @@
89 89 NextState <= STATE_READY;
90 90 end
91 91 endcase
  92 + end
92 93  
  94 + always @(*)
  95 + begin
93 96 o_CORE_Valid <= FALSE;
94 97 o_CORE_Data_Read <= FALSE;
95 98 o_CORE_Last <= FALSE;