Venkataram Edavamadathil Sivaram / supermips

Download as
Browse Code ยป

Commit b3d89846634cb2d8af4b0d901e0a0b8531f5c9e5

Authored by Sankara Ramesh
1 parent 294bafd806
Exists in master and in 2 other branches baseline_v3.2, baseline_v3.3

updating icache sizes

Showing 2 changed files with 2 additions and 2 deletions Side-by-side Diff

mips_cpu/mips_core/d_cache.sv View file @ b3d8984
... ... @@ -36,7 +36,7 @@
36 36 endinterface
37 37  
38 38 module d_cache #(
39   - parameter INDEX_WIDTH = 8,
  39 + parameter INDEX_WIDTH = 6,
40 40 parameter BLOCK_OFFSET_WIDTH = 2,
41 41 parameter ASSOCIATIVITY = 2
42 42 )(
mips_cpu/mips_core/i_cache.sv View file @ b3d8984
... ... @@ -25,7 +25,7 @@
25 25 `include "mips_core.svh"
26 26  
27 27 module i_cache #(
28   - parameter INDEX_WIDTH = 8,
  28 + parameter INDEX_WIDTH = 6,
29 29 parameter BLOCK_OFFSET_WIDTH = 2
30 30 )(
31 31 // General signals