Venkataram Edavamadathil Sivaram / supermips

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Commit 1a5e925a3a4d7a121f733756d13c315b00a1e0b4

Authored by Jiayan Dong
1 parent 6cd4595171
Exists in master and in 1 other branch baseline_v3.3

update openram version

Showing 1 changed file with 5 additions and 3 deletions Inline Diff

mips_cpu/synth/Makefile View file @ 1a5e925
.PHONY: clean all rams syn sta 1 1 .PHONY: clean all rams syn sta
2 2
configs= 3 3 configs=
ifneq (clean,$(MAKECMDGOALS)) 4 4 ifneq (clean,$(MAKECMDGOALS))
include configs.mk 5 5 include configs.mk
endif 6 6 endif
7 7
8 open_RAM=OpenRAM-1.2.46
9
ram_targets=$(configs:%=build/sram_%_freepdk45_analytical_TT_1p0V_25C.lib) 8 10 ram_targets=$(configs:%=build/sram_%_freepdk45_analytical_TT_1p0V_25C.lib)
9 11
all: netlist.v 10 12 all: netlist.v
11 13
mips_core.v: ../mips_core/*.sv 12 14 mips_core.v: ../mips_core/*.sv
$(CSE148_TOOLS)/sv2v/bin/sv2v -Imips_core ../mips_core/*.sv > $@ 13 15 $(CSE148_TOOLS)/sv2v/bin/sv2v -Imips_core ../mips_core/*.sv > $@
14 16
hierarchy.json: mips_core.v 15 17 hierarchy.json: mips_core.v
bash -c "source $(CSE148_TOOLS)/oss-cad-suite/environment && yosys -s hierarchy.ys -l hierarchy.log -t" 16 18 bash -c "source $(CSE148_TOOLS)/oss-cad-suite/environment && yosys -s hierarchy.ys -l hierarchy.log -t"
17 19
configs.mk synthesis.ys sram.v timing.sta: hierarchy.json generate.py 18 20 configs.mk synthesis.ys sram.v timing.sta: hierarchy.json generate.py
python3 generate.py 19 21 python3 generate.py
20 22
rams: $(ram_targets) 21 23 rams: $(ram_targets)
22 24
build/sram_%_freepdk45_analytical_TT_1p0V_25C.lib : config.py 23 25 build/sram_%_freepdk45_analytical_TT_1p0V_25C.lib : config.py
env RAM_CONFIG="$*" \ 24 26 env RAM_CONFIG="$*" \
FREEPDK45=$(CSE148_TOOLS)/FreePDK45 \ 25 27 FREEPDK45=$(CSE148_TOOLS)/FreePDK45 \
OPENRAM_HOME=$(CSE148_TOOLS)/OpenRAM-1.2.45/compiler \ 26 28 OPENRAM_HOME=$(CSE148_TOOLS)/$(open_RAM)/compiler \
OPENRAM_TECH=$(CSE148_TOOLS)/OpenRAM-1.2.45/technology \ 27 29 OPENRAM_TECH=$(CSE148_TOOLS)/$(open_RAM)/technology \
python3 $(CSE148_TOOLS)/OpenRAM-1.2.45/sram_compiler.py config 28 30 python3 $(CSE148_TOOLS)/$(open_RAM)/sram_compiler.py config
29 31
netlist.v: mips_core.v $(ram_targets) synthesis.ys 30 32 netlist.v: mips_core.v $(ram_targets) synthesis.ys
bash -c "source $(CSE148_TOOLS)/oss-cad-suite/environment && yosys -s synthesis.ys -l synthesis.log -t" 31 33 bash -c "source $(CSE148_TOOLS)/oss-cad-suite/environment && yosys -s synthesis.ys -l synthesis.log -t"
32 34
syn: netlist.v 33 35 syn: netlist.v
34 36
sta: netlist.v timing.sta $(ram_targets) 35 37 sta: netlist.v timing.sta $(ram_targets)
$(CSE148_TOOLS)/OpenSTA/app/sta timing.sta 36 38 $(CSE148_TOOLS)/OpenSTA/app/sta timing.sta