Commit 1a5e925a3a4d7a121f733756d13c315b00a1e0b4
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update openram version
Showing 1 changed file with 5 additions and 3 deletions Side-by-side Diff
mips_cpu/synth/Makefile
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1a5e925
| ... | ... | @@ -5,6 +5,8 @@ |
| 5 | 5 | include configs.mk |
| 6 | 6 | endif |
| 7 | 7 | |
| 8 | +open_RAM=OpenRAM-1.2.46 | |
| 9 | + | |
| 8 | 10 | ram_targets=$(configs:%=build/sram_%_freepdk45_analytical_TT_1p0V_25C.lib) |
| 9 | 11 | |
| 10 | 12 | all: netlist.v |
| ... | ... | @@ -23,9 +25,9 @@ |
| 23 | 25 | build/sram_%_freepdk45_analytical_TT_1p0V_25C.lib : config.py |
| 24 | 26 | env RAM_CONFIG="$*" \ |
| 25 | 27 | FREEPDK45=$(CSE148_TOOLS)/FreePDK45 \ |
| 26 | - OPENRAM_HOME=$(CSE148_TOOLS)/OpenRAM-1.2.45/compiler \ | |
| 27 | - OPENRAM_TECH=$(CSE148_TOOLS)/OpenRAM-1.2.45/technology \ | |
| 28 | - python3 $(CSE148_TOOLS)/OpenRAM-1.2.45/sram_compiler.py config | |
| 28 | + OPENRAM_HOME=$(CSE148_TOOLS)/$(open_RAM)/compiler \ | |
| 29 | + OPENRAM_TECH=$(CSE148_TOOLS)/$(open_RAM)/technology \ | |
| 30 | + python3 $(CSE148_TOOLS)/$(open_RAM)/sram_compiler.py config | |
| 29 | 31 | |
| 30 | 32 | netlist.v: mips_core.v $(ram_targets) synthesis.ys |
| 31 | 33 | bash -c "source $(CSE148_TOOLS)/oss-cad-suite/environment && yosys -s synthesis.ys -l synthesis.log -t" |