Venkataram Edavamadathil Sivaram / supermips

Authored by Sankara Ramesh 2023-04-04 21:25:16 -0700

Exists in master and in 2 other branches

Showing 2 changed files with 10 additions and 6 deletions Side-by-side Diff

1	1	/*
2	2	* d_cache.sv
3	3	* Author: Zinsser Zhang
4		- * Last Revision: 03/13/2022
	4	+ * Revision : Sankara
	5	+ * Last Revision: 04/04/2023
5	6	*
6		- * This is a direct-mapped data cache. Line size and depth (number of lines) are
	7	+ * This is a 2-way set associative data cache. Line size and depth (number of lines) are
7	8	* set via INDEX_WIDTH and BLOCK_OFFSET_WIDTH parameters. Notice that line size
8	9	* means number of words (each consist of 32 bit) in a line. Because all
9	10	* addresses in mips_core are 26 byte addresses, so the sum of TAG_WIDTH,
10	11	* INDEX_WIDTH and BLOCK_OFFSET_WIDTH is `ADDR_WIDTH - 2.
	12	+ * The ASSOCIATIVITY is fixed at 2 because of the replacement policy. The replacement
	13	+ * policy also needs changes when changing the ASSOCIATIVITY
11	14	*
12	15	* Typical line sizes are from 2 words to 8 words. The memory interfaces only
13	16	* support up to 8 words line size.
...	...	@@ -36,7 +39,7 @@
36	39	endinterface
37	40
38	41	module d_cache #(
39		- parameter INDEX_WIDTH = 6,
	42	+ parameter INDEX_WIDTH = 6, // 2 * 1 KB Cache Size
40	43	parameter BLOCK_OFFSET_WIDTH = 2,
41	44	parameter ASSOCIATIVITY = 2
42	45	)(

1	1	/*
2	2	* i_cache.sv
3		- * Author: Zinsser Zhang
4		- * Last Revision: 03/13/2022
	3	+ * Author: Zinsser Zhang
	4	+ * Revision : Sankara
	5	+ * Last Revision: 04/04/2023
5	6	*
6	7	* This is a direct-mapped instruction cache. Line size and depth (number of
7	8	* lines) are set via INDEX_WIDTH and BLOCK_OFFSET_WIDTH parameters. Notice that
...	...	@@ -25,7 +26,7 @@
25	26	`include "mips_core.svh"
26	27
27	28	module i_cache #(
28		- parameter INDEX_WIDTH = 6,
	29	+ parameter INDEX_WIDTH = 6, // 1 KB Cahe size
29	30	parameter BLOCK_OFFSET_WIDTH = 2
30	31	)(
31	32	// General signals