Venkataram Edavamadathil Sivaram / supermips

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Commit 1329579e042995ecabcf7ee9905d63d1e751b0ae

Authored by zinsser
1 parent 0da65f785c
Exists in master and in 5 other branches baseline_v2.3, baseline_v3.0, baseline_v3.2, baseline_v3.3, origin/baseline_v2.3

Report the number of instructions and the number of cycles at the end of a full simulation.

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mips_cpu/testbench.sv View file @ 1329579
/* 1 1 /*
* testbench.sv 2 2 * testbench.sv
* Author: Zinsser Zhang 3 3 * Author: Zinsser Zhang
* Last Revision: 04/08/2018 4 4 * Last Revision: 04/08/2018
* 5 5 *
* This is the simulation testbench. It connects mips_cpu to a sdram model, and 6 6 * This is the simulation testbench. It connects mips_cpu to a sdram model, and
* generates top-level input clock and signals. 7 7 * generates top-level input clock and signals.
*/ 8 8 */
`timescale 1 ns / 1 ps 9 9 `timescale 1 ns / 1 ps
`include "mips_cpu.svh" 10 10 `include "mips_cpu.svh"
11 11
module testbench (); 12 12 module testbench ();
// Connections to mips_cpu 13 13 // Connections to mips_cpu
logic CLOCK_50; 14 14 logic CLOCK_50;
15 15
logic [12:0] DRAM_ADDR; 16 16 logic [12:0] DRAM_ADDR;
logic [1:0] DRAM_BA; 17 17 logic [1:0] DRAM_BA;
logic DRAM_CAS_N; 18 18 logic DRAM_CAS_N;
logic DRAM_CKE; 19 19 logic DRAM_CKE;
logic DRAM_CLK; 20 20 logic DRAM_CLK;
logic DRAM_CS_N; 21 21 logic DRAM_CS_N;
wire [15:0] DRAM_DQ; 22 22 wire [15:0] DRAM_DQ;
logic DRAM_LDQM; 23 23 logic DRAM_LDQM;
logic DRAM_RAS_N; 24 24 logic DRAM_RAS_N;
logic DRAM_UDQM; 25 25 logic DRAM_UDQM;
logic DRAM_WE_N; 26 26 logic DRAM_WE_N;
27 27
logic [9:0] SW; 28 28 logic [9:0] SW;
29 29
mips_cpu DUT ( 30 30 mips_cpu DUT (
.CLOCK_50, 31 31 .CLOCK_50,
32 32
.DRAM_ADDR, 33 33 .DRAM_ADDR,
.DRAM_BA, 34 34 .DRAM_BA,
.DRAM_CAS_N, 35 35 .DRAM_CAS_N,
.DRAM_CKE, 36 36 .DRAM_CKE,
.DRAM_CLK, 37 37 .DRAM_CLK,
.DRAM_CS_N, 38 38 .DRAM_CS_N,
.DRAM_DQ, 39 39 .DRAM_DQ,
.DRAM_LDQM, 40 40 .DRAM_LDQM,
.DRAM_RAS_N, 41 41 .DRAM_RAS_N,
.DRAM_UDQM, 42 42 .DRAM_UDQM,
.DRAM_WE_N, 43 43 .DRAM_WE_N,
44 44
.SW 45 45 .SW
); 46 46 );
47 47
sdr SDR ( 48 48 sdr SDR (
.Dq (DRAM_DQ), 49 49 .Dq (DRAM_DQ),
.Addr (DRAM_ADDR), 50 50 .Addr (DRAM_ADDR),
.Ba (DRAM_BA), 51 51 .Ba (DRAM_BA),
.Clk (DRAM_CLK), 52 52 .Clk (DRAM_CLK),
.Cke (DRAM_CKE), 53 53 .Cke (DRAM_CKE),
.Cs_n (DRAM_CS_N), 54 54 .Cs_n (DRAM_CS_N),
.Ras_n (DRAM_RAS_N), 55 55 .Ras_n (DRAM_RAS_N),
.Cas_n (DRAM_CAS_N), 56 56 .Cas_n (DRAM_CAS_N),
.We_n (DRAM_WE_N), 57 57 .We_n (DRAM_WE_N),
.Dqm ({DRAM_UDQM, DRAM_LDQM}) 58 58 .Dqm ({DRAM_UDQM, DRAM_LDQM})
); 59 59 );
60 60
// Generate reference clock 61 61 // Generate reference clock
always 62 62 always
begin 63 63 begin
#10 CLOCK_50 = ~CLOCK_50; 64 64 #10 CLOCK_50 = ~CLOCK_50;
end 65 65 end
66 66
initial 67 67 initial
begin 68 68 begin
CLOCK_50 = 1'b0; 69 69 CLOCK_50 = 1'b0;
SW[0] = 1'b0; // Hard reset 70 70 SW[0] = 1'b0; // Hard reset
SW[1] = 1'b0; // Soft reset 71 71 SW[1] = 1'b0; // Soft reset
72 72
repeat (10) @(posedge CLOCK_50); // Wait for 10 cycles 73 73 repeat (10) @(posedge CLOCK_50); // Wait for 10 cycles
SW[0] = 1'b1; // Release hard reset 74 74 SW[0] = 1'b1; // Release hard reset
75 75
/* 76 76 /*
* Memory controller is set to wait 1us after a hard reset for the 77 77 * Memory controller is set to wait 1us after a hard reset for the
* hardware memory to stabilize. In real world this should be 100us. 78 78 * hardware memory to stabilize. In real world this should be 100us.
* Wait 2us before releasing the soft reset. 79 79 * Wait 2us before releasing the soft reset.
*/ 80 80 */
#2000 @(posedge DUT.clk); 81 81 #2000 @(posedge DUT.clk);
// Hack binary code into sdram's bank0. Please change the path 82 82 // Hack binary code into sdram's bank0. Please change the path
$readmemh("../../../hexfiles/nqueens.16bit.bank0.hex", SDR.Bank0); 83 83 $readmemh("../../../hexfiles/nqueens.16bit.bank0.hex", SDR.Bank0);
$readmemh("../../../hexfiles/nqueens.16bit.bank1.hex", SDR.Bank1); 84 84 $readmemh("../../../hexfiles/nqueens.16bit.bank1.hex", SDR.Bank1);
// Release soft reset 85 85 // Release soft reset
SW[1] = 1'b1; 86 86 SW[1] = 1'b1;
87 87
/* 88 88 /*